Semiconductor device, display system, and electronic device

ABSTRACT

To provide a novel semiconductor device or display system. To provide a semiconductor device or display system that can display stereoscopic images. 
     A signal generation unit has a function of with the use of artificial intelligence, obtaining information on a scene of an image and information on a depth of the image and correcting image data on the basis of the information so that a stereoscopic effect is emphasized. An image signal obtained by the correction of the image data is supplied to a display unit, so that a stereoscopic image can be displayed on a display region

TECHNICAL FIELD

One embodiment of the present invention relates to a semiconductordevice, a display system, and an electronic device.

Note that one embodiment of the present invention is not limited to theabove technical field. Examples of the technical field of one embodimentof the present invention disclosed in this specification and the likeinclude a semiconductor device, a display device, a light-emittingdevice, a power storage device, a memory device, a display system, anelectronic device, a lighting device, an input device, an input/outputdevice, a driving method thereof, and a manufacturing method thereof.

In this specification and the like, a semiconductor device generallymeans a device that can function by utilizing semiconductorcharacteristics. A transistor, a semiconductor circuit, an arithmeticdevice, a memory device, and the like are embodiments of thesemiconductor device. In addition, a display device, an imaging device,an electro-optical device, a power generation device (including a thinfilm solar cell, an organic thin film solar cell, and the like), and anelectronic device may include a semiconductor device.

BACKGROUND ART

Uses for a display device are diversified in recent years, and forexample, the display device is used for a portable information terminal,a television device for home use (also referred to as a TV or atelevision receiver), digital signage, a PID (Public InformationDisplay), and the like.

Examples of the display device include, typically, a light-emittingdevice including a light-emitting element such as an organic EL (ElectroLuminescence) element or a light-emitting diode (LED), a liquid crystaldisplay device, and electronic paper performing display by anelectrophoretic method or the like. Patent Document 1 discloses adisplay device that can provide a stereoscopic effect or a sense ofdepth by using a display unit having a curved surface.

PRIOR ART DOCUMENT

[Patent Document]

[Patent Document 1] Japanese Published Patent Application No.2016-110117

SUMMARY OF THE INVENTION Problems to be Solved by the Invention

An object of one embodiment of the present invention is to provide anovel semiconductor device or display system. Another object of oneembodiment of the present invention is to provide a semiconductor deviceor display system that can display stereoscopic images. Another objectof one embodiment of the present invention is to provide a versatilesemiconductor device or display system. Another object of one embodimentof the present invention is to provide a semiconductor device or displaysystem with a simplified structure. Another object of one embodiment ofthe present invention is to provide a semiconductor device or displaysystem with low power consumption.

Note that one embodiment of the present invention does not necessarilyachieve all the above objects and only needs to achieve at least one ofthe objects. The description of the above objects does not preclude theexistence of other objects. Objects other than the above will beapparent from the description of the specification, the claims, thedrawings, and the like, and objects other than the above can be derivedfrom the description of the specification, the claims, the drawings, andthe like.

Means for Solving the Problems

A semiconductor device of one embodiment of the present inventionincludes a first obtaining unit, a second obtaining unit, a selectionunit, and a correction unit. The first obtaining unit has a function ofobtaining first information on a scene of an image. The second obtainingunit has a function of obtaining second information on a depth of animage. The selection unit has a function of selecting a depth mapsuitable for an emphasis of a stereoscopic effect of an image on thebasis of the first information and the second information. Thecorrection unit has a function of correcting image data on the basis ofthe depth map. The selection unit includes a neural network. The secondinformation is input to an input layer of the neural network. Aselection result of the depth map is output from an output layer of theneural network.

In the semiconductor device of one embodiment of the present invention,the first obtaining unit may have a function of obtaining the firstinformation using machine learning, and the second obtaining unit mayhave a function of obtaining the second information using machinelearning.

In the semiconductor device of one embodiment of the present invention,the correction unit may include a conversion unit and an emphasis unit,the correction unit has a function of correcting image data, and theemphasis unit may have a function of performing processing foremphasizing a stereoscopic effect on the image data corrected by thecorrection unit.

In the semiconductor device of one embodiment of the present invention,the neural network may include a product-sum operation element, theproduct-sum operation element may include a memory circuit including afirst transistor, a second transistor, and a capacitor, one of a sourceand a drain of the first transistor may be electrically connected to agate of the second transistor and the capacitor, and the firsttransistor may include a metal oxide in a channel formation region.

A display system of one embodiment of the present invention includes asignal generation unit and a display unit each including the abovesemiconductor device. The signal generation unit has a function ofgenerating an image signal using the corrected image data. The displayunit has a function of displaying an image on the basis of the imagesignal.

In the display system of one embodiment of the present invention, thedisplay unit may include a display panel, and the display panel may haveflexibility.

A display system of one embodiment of the present invention includes adisplay unit and a signal generation unit. The display unit includes adisplay panel. The display panel includes a display element and a firsttransistor. The display element is electrically connected to the firsttransistor. The display element includes a micro light-emitting diode(hereinafter, also referred to as a micro LED). The first transistorincludes a metal oxide in a channel formation region. The signalgeneration unit has a function of correcting image data and a functionof generating an image signal using the corrected image data. Thedisplay unit has a function of displaying an image on the basis of theimage signal.

A display system of one embodiment of the present invention includes adisplay unit and a signal generation unit. The display unit includes adisplay panel. The display panel includes a display element. The displayelement includes a micro light-emitting diode. The signal generationunit includes a first transistor. The first transistor includes a metaloxide in a channel formation region. The signal generation unit has afunction of correcting image data and a function of generating an imagesignal using the corrected image data. The display unit has a functionof displaying an image on the basis of the image signal.

A display system of one embodiment of the present invention includes adisplay unit and a signal generation unit. The display unit includes adisplay panel. The display panel includes a display element and a firsttransistor. The display element is electrically connected to the firsttransistor. The display element includes a micro light-emitting diode.The first transistor includes a metal oxide in a channel formationregion. The signal generation unit includes a second transistor. Thesecond transistor includes a metal oxide in a channel formation region.The signal generation unit has a function of correcting image data and afunction of generating an image signal using the corrected image data.The display unit has a function of displaying an image on the basis ofthe image signal.

In the display system of one embodiment of the present invention, thesignal generation unit may include a first obtaining unit, a secondobtaining unit, a selection unit, and a correction unit. The firstobtaining unit may have a function of obtaining first information on ascene of an image. The second obtaining unit may have a function ofobtaining second information on a depth of an image. The selection unitmay have a function of selecting a depth map suitable for an emphasis ofa stereoscopic effect of an image on the basis of the first informationand the second information. The correction unit may have a function ofcorrecting image data on the basis of the depth map. The selection unitmay include a neural network. The second information may be input to aninput layer of the neural network. A selection result of the depth mapmay be output from an output layer of the neural network.

In the display system of one embodiment of the present invention, thefirst obtaining unit may have a function of obtaining the firstinformation using machine learning, and the second obtaining unit mayhave a function of obtaining the second information using machinelearning.

In the display system of one embodiment of the present invention, thecorrection unit may include a conversion unit and an emphasis unit, andthe emphasis unit may have a function of performing processing foremphasizing a stereoscopic effect on the image data corrected by thecorrection unit.

In the display system of one embodiment of the present invention, theneural network may include a product-sum operation element. Theproduct-sum operation element may include a memory circuit including athird transistor, a fourth transistor, and a capacitor. One of a sourceand a drain of the third transistor may be electrically connected to agate of the fourth transistor and the capacitor. The third transistormay include a metal oxide in a channel formation region.

An electronic device of one embodiment of the present invention includesany of the above-described display systems.

Effect of the Invention

One embodiment of the present invention can provide a novelsemiconductor device or display system. Another embodiment of thepresent invention can provide a semiconductor device or display systemthat can display stereoscopic images. Another embodiment of the presentinvention can provide a versatile semiconductor device or displaysystem. Another embodiment of the present invention can provide asemiconductor device or display system with a simplified structure.Another embodiment of the present invention can provide a semiconductordevice or display system with low power consumption.

Note that the description of these effects does not preclude theexistence of other effects. Moreover, one embodiment of the presentinvention does not necessarily have all of these effects. Effects otherthan the above will be apparent from the description of thespecification, the claims, the drawings, and the like, and effects otherthan the above can be derived from the description of the specification,the claims, the drawings, and the like.

BRIEF DESCRIPTION OF DRAWINGS

FIG. 1 A diagram illustrating a structure example of a display system.

FIGS. 2A-2B Diagrams illustrating an example of scene information.

FIG. 3 A diagram illustrating an example of depth information.

FIGS. 4A-4B Diagrams illustrating examples of a depth map.

FIGS. 5A-5B Diagrams illustrating structure examples of a selectionunit.

FIG. 6 A diagram illustrating a structure example of a neural network.

FIGS. 7A-7B4 Diagrams illustrating a structure example of a generationunit and examples of emphasis processing.

FIG. 8 A diagram illustrating a structure example of a learning unit.

FIGS. 9A-9C Diagrams illustrating structure examples of a neuralnetwork.

FIG. 10 A flow chart.

FIG. 11 A diagram illustrating a structure example of an arithmeticdevice.

FIG. 12 A diagram illustrating a structure example of a semiconductordevice.

FIG. 13 A diagram illustrating a structure example of a memory circuit.

FIG. 14 A diagram illustrating a structure example of memory cells.

FIG. 15 A diagram illustrating structure examples of circuits.

FIG. 16 A timing chart.

FIGS. 17A-17C Diagrams illustrating a structure example of a transistor.

FIG. 18 A diagram showing an energy band structure.

FIG. 19 A diagram illustrating a structure example of a semiconductordevice.

FIGS. 20A-20C Diagrams illustrating structure examples of a displaydevice.

FIG. 21 A diagram illustrating a structure example of a display device.

FIGS. 22A-22C Diagrams illustrating a structure example of a displaypanel.

FIG. 23 A diagram illustrating a structure example of a display device.

FIG. 24 A diagram illustrating a structure example of a display device.

FIG. 25 A diagram illustrating a structure example of a display device.

FIGS. 26A1-26B2 Diagrams illustrating structure examples of displaydevices.

FIGS. 27A1-27B Diagrams illustrating structure examples of displaydevices.

FIGS. 28A-28B Diagrams illustrating structure examples of electronicdevices.

FIGS. 29A-29B Diagrams illustrating structure examples of electronicdevices.

FIG. 30 A diagram illustrating a structure example of a vehicle.

MODE FOR CARRYING OUT THE INVENTION

Embodiments of the present invention are described below in detail withreference to the drawings. Note that the present invention is notlimited to the description in the following embodiments, and it iseasily understood by those skilled in the art that the modes and detailscan be changed in various ways without departing from the spirit andscope of the present invention. Thus, the present invention should notbe interpreted as being limited to the following description of theembodiments.

In this specification and the like, a metal oxide means an oxide ofmetal in a broad sense. Metal oxides are classified into an oxideinsulator, an oxide conductor (including a transparent oxide conductor),an oxide semiconductor (also simply referred to as an OS), and the like.When a metal oxide is used in a channel region of a transistor, forexample, the metal oxide is called an oxide semiconductor in some cases.That is, when a metal oxide has at least one of an amplifying function,a rectifying function, and a switching function, the metal oxide can becalled a metal oxide semiconductor, or an OS for short. Hereinafter, atransistor containing a metal oxide in a channel region is also referredto as an OS transistor.

In this specification and the like, a metal oxide containing nitrogen isalso called a metal oxide in some cases. Moreover, a metal oxidecontaining nitrogen may be called a metal oxynitride. The details of ametal oxide are described later.

In the case where there is an explicit description X and Y areconnected, the case where X and Y are electrically connected, the casewhere X and Y are functionally connected, and the case where X and Y aredirectly connected are disclosed in this specification and the like.Accordingly, without being limited to a predetermined connectionrelation, for example, a connection relation shown in drawings or texts,a connection relation other than one shown in drawings or texts isincluded in the drawings or the texts. Here, X and Y each denote anobject (e.g., a device, an element, a circuit, a wiring, an electrode, aterminal, a conductive film, or a layer).

An example of the case where X and Y are directly connected is the casewhere an element that allows an electrical connection between X and Y(e.g., a switch, a transistor, a capacitor, an inductor, a resistor, adiode, a display element, a light-emitting element, or a load) is notconnected between X and Y, and is the case where X and Y are connectedwithout the element that allows the electrical connection between X andY (e.g., a switch, a transistor, a capacitor, an inductor, a resistor, adiode, a display element, a light-emitting element, or a load) providedtherebetween.

An example of the case where X and Y are electrically connected is thecase where one or more elements that allow an electrical connectionbetween X and Y (e.g., a switch, a transistor, a capacitor, an inductor,a resistor, a diode, a display element, a light-emitting element, or aload) can be connected between X and Y. Note that a switch has afunction of being controlled to be turned on or off. That is, a switchhas a function of being turned on or off to control whether currentflows therethrough or not. Alternatively, a switch has a function ofselecting and changing a current path. Note that the case where X and Yare electrically connected includes the case where X and Y are directlyconnected.

An example of the case where X and Y are functionally connected is thecase where one or more circuits that allow a functional connectionbetween X and Y (e.g., a logic circuit (an inverter, a NAND circuit, aNOR circuit, or the like); a signal converter circuit (a DA convertercircuit, an AD converter circuit, a gamma correction circuit, or thelike), a potential level converter circuit (a power supply circuit (astep-up circuit, a step-down circuit, or the like), a level shiftercircuit for changing the potential level of a signal, or the like), avoltage source, a current source, a switching circuit, an amplifiercircuit (a circuit capable of increasing signal amplitude, the amount ofcurrent, or the like, an operational amplifier, a differential amplifiercircuit, a source follower circuit, a buffer circuit, or the like), asignal generator circuit, a memory circuit, or a control circuit) can beconnected between X and Y. Note that even when another circuit isprovided between X and Y, for example, X and Y are regarded as beingfunctionally connected in the case where a signal output from X istransmitted to Y. Note that the case where X and Y are functionallyconnected includes the case where X and Y are directly connected and thecase where X and Y are electrically connected.

Note that in the case where there is an explicit description X and Y areelectrically connected, the case where X and Y are electricallyconnected (that is, the case where X and Y are connected with anotherelement or another circuit provided therebetween), the case where X andY are functionally connected (that is, the case where X and Y arefunctionally connected with another circuit provided therebetween), andthe case where X and Y are directly connected (that is, the case where Xand Y are connected without another element or another circuit providedtherebetween) are disclosed in this specification and the like. That is,in the case where there is an explicit description “being electricallyconnected”, the same contents as the case where there is only anexplicit description “being connected”, are disclosed in thisspecification and the like.

Even when a drawing shows that independent components are electricallyconnected to each other, one component has functions of a plurality ofcomponents in some cases. For example, when part of a wiring alsofunctions as an electrode, one conductive film has functions of both ofthe components, the function of the wiring and the function of theelectrode. Thus, electrical connection in this specification alsoincludes such a case where one conductive film has functions of aplurality of components, in its category.

Embodiment 1

In this embodiment, a semiconductor device and a display system of oneembodiment of the present invention are described.

<Structure Example of Display System>

FIG. 1 illustrates a structure example of a display system 10. Thedisplay system 10 has a function of generating a signal for displayingan image on the basis of data received from the outside and displayingthe image using the signal. The display system 10 includes a displayunit 20, a signal generation unit 30, and an arithmetic unit 40.

Note that the display unit 20, the signal generation unit 30, and thearithmetic unit 40 can each include a semiconductor device. The displayunit 20 can include a display device, and the arithmetic unit 40 caninclude an arithmetic device. Circuits included in the signal generationunit 30 can be integrated into one integrated circuit. Thus, the displayunit 20 can be referred to as a semiconductor device or a displaydevice. The signal generation unit 30 can be referred to as asemiconductor device or an integrated circuit. The arithmetic unit 40can be referred to as a semiconductor device or an arithmetic device.

[Display Unit]

The display unit 20 includes a display region DSP. The display regionDSP has a function of displaying an image on the basis of a signal fordisplaying a predetermined image (hereinafter, also referred to as animage signal) that is input from the signal generation unit 30. Thedisplay region DSP includes a plurality of pixels pix. Here, the casewhere the display region DSP includes the pixels pix arranged in n rowsand m columns (n and m are natural numbers) is described.

The pixels pix each include a display element and have a function ofexpressing a predetermined gray level. The gray levels of the pixels pixare controlled, whereby a predetermined image is displayed on thedisplay region DSP.

Examples of the display element provided in the pixels pix include aliquid crystal element and a light-emitting element. As the liquidcrystal element, a transmissive liquid crystal element, a reflectiveliquid crystal element, a transflective liquid crystal element, or thelike can be used.

Moreover, as the display element, a shutter type MEMS (Micro ElectroMechanical Systems) element, an optical interference type MEMS element,or a display element using a microcapsule method, an electrophoreticmethod, an electrowetting method, an Electronic Liquid Powder(registered trademark) method, or the like can be used, for example. Inaddition, examples of the light-emitting element include self-luminouslight-emitting elements such as an OLED (Organic Light Emitting Diode),an LED (Light Emitting Diode), a QLED (Quantum-dot Light EmittingDiode), and a semiconductor laser.

The number of pixels pix provided in the display region DSP can befreely set. For example, pixels of 3840×2160 or more or 4096×2160 ormore are preferably provided in the case of displaying a 4K2K image onthe display region DSP. Moreover, pixels of 7680×4320 or more arepreferably provided in the case of displaying an 8K4K image on thedisplay region DSP. Furthermore, a larger number of pixels pix can beprovided in the display region DSP.

The display region DSP may have a curved surface. Accordingly, imagescan be displayed on various places. For example, the display region DSPcan be provided along a curved surface of an inside wall or an outsidewall of a building or an interior or an exterior of a vehicle.

An image to be displayed on the display unit 20 may include athree-dimensional object, scenery, or the like. However, an image thatis actually displayed on the display region DSP is expressed by imagedata of two-dimensional arrangement of n×m, and thus is displayed as atwo-dimensional image. Therefore, in order to display athree-dimensional image with a stereoscopic effect on the display regionDSP, it is preferable to perform image processing for emphasizing thestereoscopic effect. The stereoscopic effect of a two-dimensional imagecan be emphasized by, for example, control of the luminance of theimage, a size of an object in the image, aerial perspective (blueness inthe background, a blur of an outline, or the like), a shadow, acontrast, or the like.

Here, in one embodiment of the present invention, an image signalemphasizing a stereoscopic effect of an image is generated usingartificial intelligence (AI). Specifically, the signal generation unit30 has a function of, with the use of artificial intelligence, obtaininginformation on a scene of an image (hereinafter, also referred to asscene information) and information on a depth of an image (hereinafter,also referred to as depth information) and correcting image data on thebasis of the information so that a stereoscopic effect is emphasized. Bysupplying an image signal, which is obtained by the correction of theimage data, to the display unit 20, a stereoscopic image can bedisplayed on the display region DSP.

Note that artificial intelligence is a general term of computers thatimitate the intelligence of human beings. In this specification and thelike, artificial intelligence includes a computer that performs anarithmetic operation using machine learning. Examples of the machinelearning include a support vector machine (SVM) and boosting. In thisspecification and the like, artificial intelligence includes anartificial neural network (ANN). The artificial neural network is acircuit that imitates a neural network including neurons and synapses.In this specification and the like, the term “neural network”particularly refers to an artificial neural network. Hereinafter, thesignal generation unit 30 including artificial intelligence isdescribed.

[Structure Example of Signal Generation Unit]

The signal generation unit 30 has a function of generating an imagesignal on the basis of data D input from the outside. The signalgeneration unit 30 includes a receiving unit RCV, an obtaining unit SA,an obtaining unit DA, a selection unit SP, a correction unit CP, animage processing unit IP, and an output unit OP. Each of these units caninclude a circuit.

The receiving unit RCV has a function of receiving the data D input fromthe outside and performing signal processing as appropriate. Forexample, the receiving unit RCV has a function of performingdemodulation of the data D, analog-digital conversion, decoding, and thelike. A broadcast signal modulated by a predetermined mode and encoded,or the like is input to the receiving unit RCV. Note that the data D maybe received with or without a wire.

Image data (data ID) corresponding to an image displayed on the displayunit 20 is generated by the signal processing by the receiving unit RCVand is output to the obtaining unit SA and the obtaining unit DA.

The obtaining unit SA has a function of obtaining scene information onan image corresponding to the data ID. Examples of scene informationinclude information on the entire structure of an image, information onan object included in an image, and information on situations (place,time, and the like) of an image. Specific examples of situations of animage include information on whether an image is an indoor image or anoutdoor image and information on whether an image is a dawn image, adaytime image, an evening image, or a night image.

FIG. 2 illustrates an example of scene information obtained by theobtaining unit SA.

FIG. 2(A) illustrates an example of an image IMG expressed using thedata ID. When the data ID is input to the obtaining unit SA, theobtaining unit SA recognizes an object included in the image IMG. FIG.2(B) illustrates a state where information on the existence of abuilding, a tree, and a human in the image IMG is obtained by the objectrecognition by the obtaining unit SA.

Furthermore, information on the situation of the image IMG may beobtained by the obtaining unit SA. FIG. 2(B) illustrates a state whereinformation that the image IMG is an outdoor image in the daytime(outdoor daytime) is obtained by the obtaining unit SA.

The above scene information is obtained by the obtaining unit SA andoutput to the selection unit SP as data Ds.

The obtaining unit DA has a function of obtaining depth information onan image corresponding to the data ID. Examples of depth informationinclude a size of an object in an image, a distance between objects inan image, aerial perspective, a shadow, and a decrease in a contrast dueto air scattering. Aerial perspective is generated by light scatteringand refers to a phenomenon in which an object distant from the front isblurred and its outline is blurred and thus an image becomes bluish. Thedepth of an image can be estimated from the information.

FIG. 3 illustrates examples of depth information obtained by theobtaining unit DA. From the image IMG expressed using the data ID,heights H_(b), H_(t), and H_(h) of objects (the building, the tree, andthe human), a distance d between the objects, a shadow of the human(shading), hiding of the tree by the human (hiding), a bluish region inthe back (bluish), a blur of the outline of the building (blurring), acontrast difference between the foreground and the background(contrast), and the like are obtained as the depth information. It isrecognized from the depth information that the tree is positioned behindthe human and the building is positioned behind the tree.

The above depth information is obtained by the obtaining unit DA andoutput to the selection unit SP as data Dd.

Each of the scene information and the depth information can be obtainedusing machine learning. In that case, a feature value and the kind ofmachine learning can be freely selected. For example, in the case ofextracting a feature of an image on the basis of luminance information,a Joint Haar-like feature value, a sparse feature value, or the like canbe used as the feature value. In the case of extracting a feature of animage on the basis of edge information, a Shapelet feature value, aJoint HOG feature value, or the like can be used as the feature value.Moreover, a support vector machine (SVM), boosting, a neural network,and the like can be used for the machine learning. The feature value canalso be extracted by a neural network.

The selection unit SP has a function of selecting a depth map suitablefor the emphasis of the stereoscopic effect of an image. Specifically,the selection unit SP has a function of selecting a depth map of animage (hereinafter, also referred to as an image depth map) or a depthmap of an object included in an image (hereinafter, also referred to asan object depth map) on the basis of the scene information and the depthinformation. A plurality of image depth maps or a plurality of objectdepth maps are prepared in advance, and a depth map suitable for theemphasis of the stereoscopic effect is selected on the basis of thescene information and the depth information.

A depth map selected by the selection unit SP is used for image datacorrection. The coordinates of the image or the object included in theimage are converted in accordance with the depth map selected on thebasis of the scene information and the depth information, so that thestereoscopic effect of the image can be emphasized.

FIG. 4(A) illustrates examples of an image depth map. An image depth mapIDM is a map showing the depth of the whole image. The selection unit SPhas a function of selecting one depth map IDM that is suitable for theemphasis of the stereoscopic effect from a plurality of depth maps IDMon the basis of the data Ds and the data Dd.

FIG. 4(B) illustrates examples of an object depth map. An object depthmap ODM is a map showing the depth of a boxy object included in animage. The selection unit SP has a function of selecting one depth mapODM that is suitable for the emphasis of the stereoscopic effect from aplurality of depth maps ODM on the basis of the data Ds and the data Dd.Note that the object depth map can be selected for each object includedin the image.

In order to effectively emphasize the stereoscopic effect, the depth mapneeds to be selected properly in accordance with the contents of theimage. Here, the selection unit SP has a function of selecting a depthmap using a neural network NN1 (Inference). Thus, a suitable depth mapcan be selected using various kinds of scene information and depthinformation. FIG. 5 illustrates structure examples of the selection unitSP including the neural network NN1.

The selection unit SP illustrated in FIG. 5(A) has a function ofselecting a depth map using a plurality of neural networks NN1. Theselection unit SP includes a distribution circuit DC and N (N is aninteger of 2 or more) neural networks NN1.

The distribution circuit DC has a function of distributing the data Ddand selecting the neural network NN1 to which the data Dd is supplied.The neural network NN1 to which the data Dd is supplied is determined onthe basis of the data Ds.

The plurality of neural networks NN1 have a function of selecting thedepth map of the image or the object included in the image by theinference using the data Dd as an input data. Each of the neuralnetworks NN1[1] to NN1[N] has learned such that a depth map suitable forthe emphasis of the stereoscopic effect can be selected from a pluralityof depth maps prepared in advance. The output layers of the neuralnetworks NN1[1] to NN1[N] output data Ddm[1] to Ddm[N], respectively,that correspond to selection results.

The case where a depth map for emphasizing the stereoscopic effect of animage including a building, a tree, and a human is selected isconsidered, for example. In that case, for example, the neural networksNN1[1] to NN1[4] are used as neural networks that select depth maps ofthe whole image, the building, the tree, and the human. When the data Ddis input to the selection circuit CP, the distribution circuit DCdistributes the data Dd to the particular neural network NN1 dependingon whether the data Dd is the depth information on the whole image, thebuilding, the tree, or the human, that is, on the basis of an object ofthe depth information. Note that an object of the depth information canbe determined on the basis of the data Ds.

Specifically, when the data Dd is the depth information on the wholeimage, the data Dd is input to the neural network NN1[1]. When the dataDd is the depth information on the building, the tree, and the human,the data Dd is input to the neural networks NN1[2], NN1[3], and NN1[4].The depth maps suitable for the emphasis of the stereoscopic effect areselected using the neural networks NN1[1] to NN1[4] and are output asthe data Ddm[1] to Ddm[4].

FIG. 6 illustrates a specific structure example of the neural networkNN1. The neural network NN1 includes an input layer IL, an output layerOL, and a hidden layer (middle layer) HL. Data d₁ to d_(i) (i is anatural number) corresponding to the depth information included in thedata Dd are input to the input layer IL.

Note that the neural network NN1 may be a network including a pluralityof hidden layers HL (DNN: deep neural network). Learning in the deepneural network is referred to as deep learning in some cases. The outputlayer OL, the input layer IL, and the hidden layer HL each include aplurality of units (neuron circuits), and output from units is suppliedto units provided in different layers through weights (connectionstrength).

Note that the weight coefficient of the neural network NN1 can be inputfrom the outside of the signal generation unit 30. Specifically, aweight coefficient W calculated by the arithmetic unit 40 is supplied tothe selection unit SP, and the neural network NN1 has a function ofstoring the weight coefficient W.

The function of selecting a depth map suitable for the stereoscopicemphasis on the basis of the depth information (data d₁ to d_(i)) isadded to the neural network NN1 by learning. When the data d₁ to d_(i)are input to the input layer of the neural network NN1, arithmeticprocessing is performed in each layer. The arithmetic processing in eachlayer is performed by, for example, product-sum operation of output fromthe units in the previous layer and weight coefficients. Note thatconnection between the layers may be full connection in which all theunits are connected or partial connection in which some of the units areconnected. Then, the selection results of the depth map are output fromthe output layer OL as data dm₁ to dm_(j) (j is a natural number).

The data dm₁ to dm_(j) each correspond to a particular depth map. Thevalue of the data dm can correspond to the probability that thecorresponding depth map is suitable for the stereoscopic emphasis. Sucha structure can be obtained when the number of units in the output layerOL is j and a softmax function or the like is used as an activationfunction of the output layer OL. The data Ddm, which has the highestvalue among the data dm₁ to dm_(j), corresponds to the selection resultof the depth map, and the selected depth map is output to the correctionunit CP as the data Ddm. In this manner, a particular depth map suitablefor the emphasis of the stereoscopic effect is selected from j depthmaps.

The use of a neural network in the selection unit SP makes it possibleto select a suitable depth map on the basis of the combination ofunknown depth information. Therefore, the selection unit SP can havehigher versatility.

Note that a plurality of depth maps may be selected using one neuralnetwork NN1. FIG. 5(B) illustrates a structure example in which the dataDd is sequentially input to one neural network NN1. Note that the neuralnetwork NN1 illustrated in FIG. 5(B) is connected to a memory circuitMCW.

When the data Dd is input to the neural network NN1, the memory circuitMCW supplies the weight coefficient W suitable for the data Dd to theneural network NN1 on the basis of the data Ds. That is, the weightcoefficient W stored in the neural network NN1 is changed with the dataDs every time the data Dd is input. For example, when N sets of theweight coefficients W are stored in the memory circuit MCW and oneweight coefficient W is supplied to the neural network NN1 in accordancewith the data Ds, N kinds of depth maps can be selected as in FIG. 5(A).This can reduce the number of neural networks NN1 and can simplify thestructure of the signal generation unit 30.

As described above, the selection unit SP can select a depth map usingthe neural network NN1. Then, the selection result of the depth map isoutput as the data Ddm to the correction unit CP illustrated in FIG. 1.

The correction unit CP has a function of correcting the data ID on thebasis of the data Ddm. Specifically, the correction unit CP has afunction of correcting the data ID to data ID′ using the depth mapselected by the selection unit SP so that the stereoscopic effect isemphasized. The correction unit CP may have a function of performingprocessing for emphasizing the stereoscopic effect (hereinafter, alsoreferred to as emphasis processing) on the data ID′.

FIG. 7(A) illustrates a structure example of the correction unit CP. Thecorrection unit CP includes a conversion unit TP and an emphasis unitEP. The data ID and the data Ddm are supplied to the conversion unit TP.

The conversion unit TP has a function of converting the data ID usingthe data Ddm. Specifically, the conversion unit TP has a function ofconverting the depth map of the image or the object included in theimage expressed using the data ID into the depth map selected by theselection unit SP. Accordingly, the data ID is converted into image datahaving an emphasized stereoscopic effect (the data ID′), and the dataID′ is output to the emphasis unit EP.

The emphasis unit EP has a function of performing emphasis processing onthe data ID′. Examples of the emphasis processing include adjustment ofluminance of an image, a size of an object in an image, aerialperspective, a shadow, and a contrast. FIGS. 7(B-1) to 7(B-4) illustratespecific examples of the emphasis processing.

FIG. 7(B-1) illustrates an example of adjusting the luminance of anobject. Increasing the gray levels toward a region positioned at thefront can emphasize the stereoscopic effect of the object. FIG. 7(B-2)illustrates an example of adjusting the shadow of the object. Theadjustment of the existence or depth of the shadow can emphasize thestereoscopic effect of the object.

FIG. 7(B-3) illustrates an example of adjusting the aerial perspective.The perspective of the whole image can be emphasized when the backgroundis made bluish and the outline of an object positioned at a distantplace is blurred. FIG. 7(B-4) illustrates an example of adjusting acontrast. The contrast of an object positioned at the front is increasedand the contrast of an object positioned at a distant place isdecreased, so that the perspective of the whole image can be emphasized.

The data ID′ with the stereoscopic effect emphasized by the emphasisunit EP is output to the image processing unit IP. Note that theemphasis unit EP can be omitted when the stereoscopic effect isemphasized only by conversion of the depth map using the conversion unitTP.

The image processing unit IP has a function of performing various kindsof image processing on the data ID′ and generating an image signal.Examples of the image processing include noise removal processing, graylevel conversion processing, tone correction processing, and luminancecorrection processing. The tone correction processing or the luminancecorrection processing can be performed with the use of gamma correctionor the like. Furthermore, the image processing unit IP may have afunction of executing pixel interpolation processing accompanyingup-conversion of the resolution, frame interpolation processingaccompanying up-conversion of the frame frequency, or the like. Theimage processing unit IP may also have a function of performingprocessing for emphasizing the outline or the perspective of the image.

Examples of the noise removal processing include removal of variousnoise such as mosquito noise that appears near the outlines ofcharacters and the like, block noise that appears in high-speed movingimages, random noise that causes flicker, and dot noise caused byup-conversion of the resolution.

The gray level conversion processing converts the gray level expressedby a signal SD to a gray level corresponding to output characteristicsof the display unit 20. For example, in the case where the number ofgray levels is increased, gradation values of pixels are interpolated toan input image with a small number of gray levels and assigned to thepixels, so that processing for smoothing a histogram can be executed. Ahigh-dynamic range (HDR) processing for increasing the dynamic range isalso included in the gray level conversion processing.

The tone correction processing corrects the tone of an image. Theluminance correction processing corrects the brightness (luminancecontrast) of an image. The luminance and tone of an image displayed onthe display unit 20 are corrected to be optimal, in accordance with thekind, luminance, or color purity of lighting of a room in which thedisplay unit 20 is provided, for example.

The pixel interpolation processing interpolates data that does notactually exist when resolution is up-converted. For example, withreference to pixels around the target pixel, data is interpolated todisplay intermediate color between the colors of the pixels.

In the case where the frame frequency of the displayed image isincreased, the frame interpolation processing generates an image for aframe that does not actually exist (interpolation frame). For example,an image for an interpolation frame that is interposed between certaintwo images is generated from a difference between the two images.Alternatively, images for a plurality of interpolation frames can begenerated between the two images. For example, when the frame frequencyof image data is 60 Hz, a plurality of interpolation frames aregenerated, and the frame frequency of an image signal output to thedisplay unit 20 can be increased twofold to 120 Hz, fourfold to 240 Hz,or eightfold to 480 Hz, for example.

An image signal is generated by image processing by the image processingunit IP, and is output to the output unit OP as the signal SD. Note thatthe image processing may be performed on the data ID that has not beeninput to the correction unit CP. Furthermore, artificial intelligencecan be used for the image processing.

The output unit OP has a function of temporarily storing the signal SDsupplied from the image processing unit IP and outputting the signal SDto the display unit 20 at a predetermined timing. Then, the display unit20 displays an image on the basis of the signal SD.

As described above, the signal generation unit 30 converts image datausing artificial intelligence, whereby the stereoscopic effect of theimage displayed on the display unit 20 can be emphasized.

[Arithmetic Unit]

The learning in the neural network NN1 can be performed using thearithmetic unit 40 provided outside the signal generation unit 30. FIG.1 illustrates the arithmetic unit 40 including a learning unit LP and amemory device MEM.

The learning in the neural network NN1 can be performed by updating theweight coefficient using depth information as learning data and a depthmap suitable for the emphasis of the stereoscopic effect as teacherdata. Here, the learning unit LP includes a neural network NN2(Learning) that has the same structure as the neural network NN1. Theneural network NN2 has a function of performing learning using a set oflearning data X (depth information) and teacher data T (suitable depthmap) as learning samples. The learning data X and the teacher data T arestored in the memory device MEM in advance and read out at the time oflearning.

The weight coefficient W of the neural network NN2 obtained by thelearning is stored in the neural network NN1 provided in the signalgeneration unit 30. Accordingly, the results of the learning in theneural network NN2 can be reflected in the neural network NN1. Learningin the neural network performed in the arithmetic unit 40 in this mannercan simplify the structure of the neural network NN1 provided in thesignal generation unit 30.

Note that in order to make the structure of the neural network NN1 andthe structure of the neural network NN2 correspond to each other, forexample, a hierarchical neural network is used for each of the neuralnetworks, and the neural networks have the same number of layers and thesame number of units in each layer.

As the arithmetic unit 40, a computer with high arithmetic processingproperties, such as a dedicated server or a cloud, can be used. Thelearning unit LP can include software. Accordingly, the computer withhigh arithmetic processing properties can be used for the learning inthe neural network NN2, and the learning results can be reflected in theneural network NN1. Thus, learning in the neural network NN1 can beefficiently performed.

FIG. 8 illustrates a structure example of the learning unit LP. Thelearning unit LP includes the neural network NN2. Note that the neuralnetwork NN2 has the same structure as the neural network NN1.

The learning data X (depth information) and the teacher data T (suitabledepth map) are stored in the memory device MEM. The learning data X andthe teacher data T are read out from the memory device MEM at the timeof the learning, the learning data X is supplied to the input layer ILof the neural network NN2, and the teacher data T is supplied to theoutput layer OL of the neural network NN2.

The neural network NN2 has a function of performing learning using thelearning data X and the teacher data T as learning samples.Specifically, first, the neural network NN2 performs inference using thelearning data X as input data, and obtains Y as output data. Note thatthe selection of the depth map is a classification problem, and theoutput data Y corresponds to an output value of a softmax function orthe like.

The weight coefficient of the neural network NN2 is updated so that anerror between the output data Y and the teacher data T becomes small.The weight coefficient can be updated using a gradient descent methodusing cross entropy as an error function, or the like. The update ofweight is repeated until the error between the output data Y and theteacher data T becomes a certain value or less. After that, similarlearning is performed using another set of the learning data X and theteacher data T. Then, the update of the weight coefficients using allsets of the learning data X and the teacher data T is completed, so thatthe learning in the neural network NN2 is completed.

Note that the allowable range of an error can be freely set. The initialvalue of the weight coefficient of the neural network NN2 may bedetermined by random numbers. The initial value of the weightcoefficient might affect the learning speed (e.g., the convergent speedof the weight coefficient and the prediction accuracy of the neuralnetwork); thus, the initial value of the weight coefficient may bechanged when the learning speed is low. Alternatively, the initial valueof the weight coefficient may be determined by pre-training.

As a result of the above learning, the weight coefficient W of theneural network NN2 after the learning can be obtained. The weightcoefficient W is supplied to and stored in the neural network NN1 in thesignal generation unit 30. Accordingly, the results of the learning inthe neural network NN2 can be reflected in the neural network NN1.

Note that the weight coefficient W is obtained for each depth map. Forexample, in the case where a depth map of an image including a building,a tree, and a human is selected, the weight coefficient for selectingthe depth map of the whole image and the weight coefficients forselecting the depth maps of the building, the tree, and the human areeach obtained by learning. Then, the plurality of obtained weightcoefficients W are supplied to different neural networks NN1 (see FIG.5(A)).

The neural network NN2 can be obtained by software written by a program.In that case, the neural network NN2 can perform learning by executionof the program.

As described above, the display system 10 of one embodiment of thepresent invention can perform learning in the neural network using thearithmetic unit 40.

<Structure Example of Neural Network>

Next, a structure example of a neural network that can be used as eachof the neural network NN1 and the neural network NN2 is described. FIG.9 illustrates structure examples of the neural network. The neuralnetwork includes neuron circuits NC and synapse circuits SC providedbetween the neuron circuits.

FIG. 9(A) illustrates a structure example of the neuron circuit NC andthe synapse circuits SC. Input data x₁ to x_(L) (L is a natural number)are input to the synapse circuits SC. In addition, the synapse circuitsSC have a function of storing a weight coefficient w_(k) (k is aninteger of 1 to L inclusive). The weight coefficient w_(k) correspondsto the connection strength between the neuron circuits NC.

When the input data x₁ to x_(L) are input to the synapse circuits SC,the sum of the products (x_(k)w_(k)) for k=1 to L (i.e., x₁w₁+x₂w₂+ . .. +x_(L)w_(L)) of input data x_(k) input to the synapse circuit SC andthe weight coefficient w_(k) stored in the synapse circuit SC, that is,a value obtained by the product-sum operation of x_(k) and w_(k) issupplied to the neuron circuit NC. When the value is larger than thethreshold θ of the neuron circuit NC, the neuron circuit NC outputs ahigh-level signal y. This phenomenon is referred to as firing of theneuron circuit NC.

FIG. 9(B) illustrates a model of a hierarchical neural network using theneuron circuits NC and the synapse circuits SC. The neural networkincludes the input layer IL, the hidden layer HL, and the output layerOL. The input layer IL includes input neuron circuits IN. The hiddenlayer HL includes hidden synapse circuits HS and hidden neuron circuitsHN. The output layer OL includes output synapse circuits OS and outputneuron circuits ON. The thresholds θ of the input neuron circuit IN, thehidden neuron circuit HN, and the output neuron circuit ON are referredto as θ_(I), θ_(H), and θ_(O), respectively.

The data d₁ to d_(i) corresponding to the depth information are suppliedto the input layer IL, and output from the input layer IL is supplied tothe hidden layer HL. Then, a value obtained by the product-sum operationof the output data of the input layer IL and the weight coefficients wthat are held in the hidden synapse circuits HS is supplied to thehidden neuron circuits HN. A value obtained by the product-sum operationof the output from the hidden neuron circuits HN and the weightcoefficients w that are held in the output synapse circuits OS issupplied to the output neuron circuits ON. Then, the data dm₁ to dm_(j)corresponding to the probability of the depth map are output from theoutput neuron circuits ON. Note that here, a softmax function is used asthe activation function of the output layer OL.

As described above, the neural network illustrated in FIG. 9(B) has afunction of calculating the probability of the depth map suitable forthe emphasis of the stereoscopic effect from the depth information. Notethat the structure in FIG. 9(B) can be used for the neural networks NN1and NN2.

A gradient descent method or the like can be used for learning in theneural network, and a backpropagation method can be used for calculationof a gradient. FIG. 9(C) illustrates a model of a neural network thatperforms supervised learning using a backpropagation method.

A backpropagation method is one of methods for changing a weightcoefficient of a synapse circuit so that an error between output data ofa neural network and teacher data becomes small. Specifically, theweight coefficient w of the hidden synapse circuit HS is changed with anerror δo that is determined on the basis of the output data (data dm₁ todm_(j)) and the teacher data (data t₁ to t_(j)). In addition, the weightcoefficient w of the synapse circuit SC in the previous stage is changedwith the amount of change in the weight coefficient w of the hiddensynapse circuit HS. In this manner, the weight coefficients of thesynapse circuits SC are sequentially changed on the basis of the teacherdata, so that the neural network NN can perform learning. Thisbackpropagation method can be used for the learning in the neuralnetwork NN2.

Note that the number of hidden layers HL is one in FIGS. 9(B) and 9(C)but the number of hidden layers HL may be two or more. Thus, deeplearning can be performed.

<Operation Example of Display System>

Next, an operation example of the display system 10 at the time when animage signal is generated using the neural network NN1 is described.FIG. 10 is a flow chart showing an operation example of the displaysystem 10.

Note that in the neural network NN1, the weight coefficient W is set inadvance by learning, and a function of selecting a depth map suitablefor the emphasis of the stereoscopic effect on the basis of depthinformation is added. For the learning in the neural network NN1, referto FIG. 8 and the like.

First, the receiving unit RCV receives the data D, and the data ID isgenerated (Step S1). Then, the data ID is output to the obtaining unitSA, the obtaining unit DA, and the correction unit CP.

When the data ID is input to the obtaining unit SA, scene information isobtained by the obtaining unit SA (Step S2). Then, the scene informationis output to the selection unit SP as the data Ds. When the data ID isinput to the obtaining unit DA, depth information is obtained by theobtaining unit DA (Step S3). Then, the depth information is output tothe selection unit SP as the data Dd. Note that the above-describedmachine learning or the like can be used to obtain the scene informationand the depth information.

Then, when the data Ds and the data Dd are input to the selection unitSP (Step S4), inference is performed by the neural network NN1corresponding to an object of the depth information (Step S5), and adepth map that is expected to be optimal for the emphasis of thestereoscopic effect is selected (Step S6). The selection result of thedepth map by the selection unit SP is output to the correction unit CPas the data Ddm. Then, the selection of the depth map is repeated in asimilar manner (NO in Step S7).

When all of the depth maps are determined (YES in Step S7), thecorrection unit CP converts the data ID into the data ID′ on the basisof the data Ddm (Step S8). Specifically, the depth map of the image orthe object included in the image that is expressed by the data ID isconverted into the depth map selected by the selection unit SP.Accordingly, the stereoscopic effect of the image or the object includedin the image is emphasized. Then, various kinds of emphasis processingand image processing are performed on the data ID′ (Steps S9 and S10),and the obtained signal SD is output from the output unit OP to thedisplay unit 20 (Step S11). Thus, a stereoscopic image is displayed onthe display unit 20.

As described above, in one embodiment of the present invention,artificial intelligence is used for obtaining the scene information andthe depth information and selecting the depth map. In this manner, theimage data can be corrected properly so that the stereoscopic effect ofthe image is emphasized, whereby the display system 10 that can displaya stereoscopic image can be obtained.

This embodiment can be combined with the description of the otherembodiments as appropriate.

Embodiment 2

In this embodiment, a structure example of the arithmetic unit describedin the above embodiment is described.

As described above, the learning unit LP included in the arithmetic unit40 can include software. In the case where the processing by thelearning unit LP is performed using a program, an arithmetic device isused as the arithmetic unit 40, and the arithmetic device can executethe program. FIG. 11 illustrates a structure example of the arithmeticdevice.

An arithmetic device 100 includes a processing device 110 and aninput/output device 120. The processing device 110 has a function ofperforming a variety of arithmetic operations such as execution of aprogram. The processing device 110 includes an arithmetic unit 111, amemory unit 112, a transmission path 113, and an interface 114. Theinput/output device 120 includes a display unit 121, an operation unit122, an input/output unit 123, and a communication unit 124.

The memory unit 112 has a function of storing a program or the like thatperforms processing of the learning unit LP. As the memory unit 112,non-transitory computer-readable memory media can be used, and forexample, a memory such as a DRAM (Dynamic Random Access Memory) or anSRAM (Static Random Access Memory) can be used. Alternatively, as thememory unit 112, a resistance change memory typified by a ReRAM(Resistive Random Access Memory) or the like, a magnetoresistive memorytypified by an MRAM (Magnetoresistive Random Access Memory) or the like,a nonvolatile memory typified by a flash memory, or the like can beused. The program stored in the memory unit 112 may include processingby the neural network NN2 illustrated in FIG. 8.

The arithmetic unit 111 has a function of performing an arithmeticoperation with use of information stored in the memory unit 112. Aprogram stored in the memory unit 112 is executed by the arithmetic unit111.

The transmission path 113 has a function of transmitting information.Information can be transmitted and received between the arithmetic unit111, the memory unit 112, and the interface 114 through the transmissionpath 113.

The interface 114 has a function of transmitting information to theinput/output device 120 and a function of receiving information outputfrom the input/output device 120.

The display unit 121 has a function of displaying an image on the basisof information input from the processing device 110. A display devicesuch as a liquid crystal display or an organic EL display can be used asthe display unit 121.

The operation unit 122 has a function of transmitting an instruction tothe processing device 110 in response to an operation by the user. Asthe operation unit 122, a keyboard, a mouse, an operation button, atouch sensor, a pointing device, or the like can be used.

The input/output unit 123 has a function of inputting information to theprocessing device 110 or outputting information input from theprocessing device 110. As the input/output unit 123, a camera, amicrophone, an external memory device, a scanner, a speaker, a printer,or the like can be used. As an external memory device, a hard disk, aremovable memory, or the like can be used.

The communication unit 124 has a function of transmitting informationinput from the processing device 110 to the outside of the arithmeticdevice 100 and a function of receiving information from the outside ofthe arithmetic device 100 and outputting the information to theprocessing device 110. As the communication unit 124, a hub, a router, amodem, or the like can be used. Information may be transmitted andreceived through wire communication or wireless communication (e.g.,radio waves or infrared light).

The weight coefficient W (see FIG. 1 and the like) obtained by executionof the program stored in the memory unit 112 can be transmitted to thesignal generation unit 30 through the communication unit 124.

This embodiment can be combined with the description of the otherembodiments as appropriate.

Embodiment 3

In this embodiment, structure examples of a semiconductor device thatcan be used in the neural networks described in the above embodiment aredescribed.

In the case where a neural network includes hardware, product-sumoperation in the neural network can be performed with the use of aproduct-sum operation element. In this embodiment, structure examples ofa semiconductor device that can be used as a product-sum operationelement in the neural network NN1 are described.

<Structure Example of Semiconductor Device>

FIG. 12 illustrates a structure example of a semiconductor device 200.The semiconductor device 200 illustrated in FIG. 12 includes a memorycircuit 210 (MEM), a reference memory circuit 220 (RMEM), a circuit 230,and a circuit 240. The semiconductor device 200 may further include acurrent supply circuit 250 (CREF).

The memory circuit 210 (MEM) includes memory cells MC such as a memorycell MC[p, q] and a memory cell MC[p+1, q]. The memory cells MC eachinclude an element that has a function of converting an input potentialinto current. As the element having such a function, an active elementsuch as a transistor can be used, for example. FIG. 12 illustrates anexample where the memory cells MC each include a transistor Tr11.

A first analog potential is input to the memory cells MC through awiring WD such as a wiring WD[q]. The first analog potential correspondsto first analog data. The memory cells MC each have a function ofgenerating a first analog current corresponding to the first analogpotential. Specifically, drain current of the transistor Tr11 that isobtained when the first analog potential is supplied to a gate of thetransistor Tr11 can be used as the first analog current. Hereinafter,current flowing in the memory cell MC[p, q] is denoted by I[p, q], andcurrent flowing in the memory cell MC[p+1, q] is denoted by I[p+1, q].

Note that the drain current of the transistor Tr11 operating in asaturation region is not dependent on voltage between its source anddrain and is controlled by the difference between its gate voltage andthreshold voltage. Thus, the transistor Tr11 desirably operates in asaturation region. The gate voltage and the voltage between the sourceand the drain of the transistor Tr11 are each appropriately set to avoltage at which the transistor Tr11 operates in a saturation region.

Specifically, in the semiconductor device 200 illustrated in FIG. 12, afirst analog potential Vx[p, q] or a potential corresponding to thefirst analog potential Vx[p, q] is input to the memory cell MC[p, q]through the wiring WD[q]. The memory cell MC[p, q] has a function ofgenerating a first analog current corresponding to the first analogpotential Vx[p, q]. This means that the current I[p, q] in the memorycell MC[p, q] corresponds to the first analog current, in this case.

Specifically, in the semiconductor device 200 illustrated in FIG. 12, afirst analog potential Vx[p+1, q] or a potential corresponding to thefirst analog potential Vx[p+1, q] is input to the memory cell MC[p+1, q]through the wiring WD[q]. The memory cell MC[p+1, q] has a function ofgenerating a first analog current corresponding to the first analogpotential Vx[p+1, q]. This means that the current I[p+1, q] in thememory cell MC[p+1, q] corresponds to the first analog current, in thiscase.

The memory cells MC each have a function of holding the first analogpotential. In other words, by holding the first analog potential, thememory cells MC each have a function of holding the first analog currentcorresponding to the first analog potential.

A second analog potential is input to the memory cells MC through awiring RW such as a wiring RW[p] or a wiring RW[p+1]. The second analogpotential corresponds to second analog data. The memory cells MC eachhave a function of adding the second analog potential or a potentialcorresponding to the second analog potential to the first analogpotential that has been held and a function of holding a third analogpotential obtained by the addition. The memory cells MC each also have afunction of generating a second analog current corresponding to thethird analog potential. In other words, by holding the third analogpotential, the memory cells MC each have a function of holding thesecond analog current corresponding to the third analog potential.

Specifically, in the semiconductor device 200 illustrated in FIG. 12, asecond analog potential Vw[p, q] is input to the memory cell MC[p, q]through the wiring RW[p]. The memory cell MC[p, q] has a function ofholding a third analog potential corresponding to the first analogpotential Vx[p, q] and the second analog potential Vw[p, q]. The memorycell MC[p, q] also has a function of generating a second analog currentcorresponding to the third analog potential. This means that the currentI[p, q] in the memory cell MC[p, q] corresponds to the second analogcurrent, in this case.

Furthermore, in the semiconductor device 200 illustrated in FIG. 12, asecond analog potential Vw[p+1, q] is input to the memory cell MC[p+1,q] through the wiring RW[p+1]. The memory cell MC[p+1, q] has a functionof holding a third analog potential corresponding to the first analogpotential Vx[p+1, q] and the second analog potential Vw[p+1, q]. Thememory cell MC[p+1, q] also has a function of generating a second analogcurrent corresponding to the third analog potential. This means that thecurrent I[p+1, q] in the memory cell MC[p+1, q] corresponds to thesecond analog current, in this case.

The current I[p, q] flows between a wiring BL[q] and a wiring VR[q]through the memory cell MC[p, q]. The current I[p+1, q] flows betweenthe wiring BL[q] and the wiring VR[q] through the memory cell MC[p+1,q]. Accordingly, a current I[q], which corresponds to the sum of thecurrent I[p, q] and the current I[p+1, q], flows between the wiringBL[q] and the wiring VR[q] through the memory cell MC[p, q] and thememory cell MC[p+1, q].

The reference memory circuit 220 (RMEM) includes memory cells MCR suchas a memory cell MCR[p] and a memory cell MCR[p+1]. A first referencepotential VPR is input to the memory cells MCR through a wiring WDREF.The memory cells MCR each have a function of generating a firstreference current corresponding to the first reference potential VPR.Note that hereinafter, current flowing in the memory cell MCR[p] isdenoted by IREF[p], and current flowing in the memory cell MCR[p+1] isdenoted by IREF[p+1].

Specifically, in the semiconductor device 200 illustrated in FIG. 12,the first reference potential VPR is input to the memory cell MCR[p]through the wiring WDREF. The memory cell MCR[p] has a function ofgenerating the first reference current corresponding to the firstreference potential VPR. This means that the current IREF[p] in thememory cell MCR[p] corresponds to the first reference current, in thiscase.

Furthermore, in the semiconductor device 200 illustrated in FIG. 12, thefirst reference potential VPR is input to the memory cell MCR[p+1]through the wiring WDREF. The memory cell MCR[p+1] has a function ofgenerating the first reference current corresponding to the firstreference potential VPR. This means that the current IREF[p+1] in thememory cell MCR[p+1] corresponds to the first reference current, in thiscase.

The memory cells MCR each have a function of holding the first referencepotential VPR. In other words, by holding the first reference potentialVPR, the memory cells MCR each have a function of holding the firstreference current corresponding to the first reference potential VPR.

Moreover, the second analog potential is input to the memory cells MCRthrough the wiring RW such as the wiring RW[p] or the wiring RW[p+1].The memory cells MCR each have a function of adding the second analogpotential or a potential corresponding to the second analog potential tothe first reference potential VPR that has been held and a function ofholding a second reference potential obtained by the addition. Thememory cells MCR each also have a function of generating a secondreference current corresponding to the second reference potential. Inother words, by holding the second reference potential, the memory cellsMCR each have a function of holding the second reference currentcorresponding to the second reference potential.

Specifically, in the semiconductor device 200 illustrated in FIG. 12,the second analog potential Vw[p, q] is input to the memory cell MCR[p]through the wiring RW[p]. The memory cell MCR[p] has a function ofholding a second reference potential corresponding to the firstreference potential VPR and the second analog potential Vw[p, q]. Thememory cell MCR[p] also has a function of generating the secondreference current corresponding to the second reference potential. Thismeans that the current IREF[p] in the memory cell MCR[p] corresponds tothe second reference current, in this case.

Furthermore, in the semiconductor device 200 illustrated in FIG. 12, thesecond analog potential Vw[p+1, q] is input to the memory cell MCR[p+1]through the wiring RW[p+1]. The memory cell MCR[p+1] has a function ofholding a second reference potential corresponding to the firstreference potential VPR and the second analog potential Vw[p+1, q]. Thememory cell MCR[p+1] also has a function of generating the secondreference current corresponding to the second reference potential. Thismeans that the current IREF[p+1] in the memory cell MCR[p+1] correspondsto the second reference current, in this case.

The current IREF[p] flows between a wiring BLREF and a wiring VRREFthrough the memory cell MCR[p]. The current IREF[p+1] flows between thewiring BLREF and the wiring VRREF through the memory cell MCR[p+1].Accordingly, a current IREF, which corresponds to the sum of the currentIREF[p] and the current IREF[p+1], flows between the wiring BLREF andthe wiring VRREF through the memory cell MCR[p] and the memory cellMCR[p+1].

The current supply circuit 250 has a function of supplying current withthe same value as the current IREF that flows through the wiring BLREFor supplying current corresponding to the current IREF to the wiring BL.In the case where the current I[q] that flows between the wiring BL[q]and the wiring VR[q] through the memory cell MC[p, q] and the memorycell MC[p+1, q] is different from the current IREF that flows betweenthe wiring BLREF and the wiring VRREF through the memory cell MCR[p] andthe memory cell MCR[p+1] and thus offset current is set as describedlater, current corresponding to the difference flows in the circuit 230or the circuit 240. The circuit 230 serves as a current source circuit,and the circuit 240 serves as a current sink circuit.

Specifically, in the case where the current I[q] is higher than thecurrent IREF, the circuit 230 has a function of generating a currentΔI[q] that corresponds to the difference between the current I[q] andthe current IREF. The circuit 230 also has a function of supplying thegenerated current ΔI[q] to the wiring BL[q]. This means that the circuit230 has a function of holding the current ΔI[q].

In the case where the current I[q] is lower than the current IREF, thecircuit 240 has a function of generating current corresponding to theabsolute value of the current ΔI[q] that corresponds the differencebetween the current I[q] and the current IREF. The circuit 240 also hasa function of drawing the generated current ΔI[q] from the wiring BL[q].This means that the circuit 240 has a function of holding the currentΔI[q].

Next, an operation example of the semiconductor device 200 illustratedin FIG. 12 is described.

First, a potential corresponding to the first analog potential is storedin the memory cell MC[p, q]. Specifically, a potential VPR−Vx[p, q],which is obtained by subtracting the first analog potential Vx[p, q]from the first reference potential VPR, is input to the memory cellMC[p, q] through the wiring WD [q]. The memory cell MC[p, q] holds thepotential VPR−Vx[p, q]. In addition, the memory cell MC[p, q] generatesthe current I[p, q] that corresponds to the potential VPR−Vx[p, q]. Thefirst reference potential VPR is, for example, a potential that ishigher than a ground potential. Specifically, the first referencepotential VPR is desirably higher than a ground potential and as high asor lower than a high-level potential VDD that is supplied to the currentsupply circuit 250.

Furthermore, the first reference potential VPR is stored in the memorycell MCR[p]. Specifically, the first reference potential VPR is input tothe memory cell MCR[p] through the wiring WDREF. The memory cell MCR[p]holds the first reference potential VPR. In addition, the memory cellMCR[p] generates the current IREF[p] that corresponds to the firstreference potential VPR.

Moreover, a potential corresponding to the first analog potential isstored in the memory cell MC[p+1, q]. Specifically, a potentialVPR−Vx[p+1, q], which is obtained by subtracting the first analogpotential Vx[p+1, q] from the first reference potential VPR, is input tothe memory cell MC[p+1, q] through the wiring WD[q]. The memory cellMC[p+1, q] holds the potential VPR−Vx[p+1, q]. In addition, the memorycell MC[p+1, q] generates the current I[p+1, q] that corresponds to thepotential VPR−Vx[p+1, q].

Furthermore, the first reference potential VPR is stored in the memorycell MCR[p+1]. Specifically, the first reference potential VPR is inputto the memory cell MCR[p+1] through the wiring WDREF. The memory cellMCR[p+1] holds the first reference potential VPR. In addition, thememory cell MCR[p+1] generates the current IREF[p+1] that corresponds tothe first reference potential VPR.

During the above operation, the potentials of the wiring RW[p] and thewiring RW[p+1] are set to a base potential. As a base potential, forexample, a ground potential or a low-level potential VSS that is lowerthan a base potential can be used. Alternatively, a potential betweenthe potential VSS and the potential VDD is preferably used as a basepotential, in which case the potential of the wiring RW can be higherthan the ground potential regardless of whether the second analogpotential Vw is positive or negative, which enables easy generation ofsignals and multiplication of either positive or negative analog data.

As a result of the above operation, current corresponding to the sum ofcurrents generated in the memory cells MC connected to the wiring BL[q]flows through the wiring BL[q]. Specifically, in FIG. 12, the currentI[q], which is the sum of the current I[p, q] generated in the memorycell MC[p, q] and the current I[p+1, q] generated in the memory cellMC[p+1, q], flows. In addition, as a result of the above operation,current corresponding to the sum of currents generated in the memorycells MCR connected to the wiring BLREF flows through the wiring BLREF.Specifically, in FIG. 12, the current IREF, which is the sum of thecurrent IREF[p] generated in the memory cell MCR[p] and the currentIREF[p+1] generated in the memory cell MCR[p+1], flows.

Next, an offset current Ioffset[q], which is obtained from thedifference between the current I[q] obtained by inputting the firstanalog potential and the current IREF obtained by inputting the firstreference potential, is held in the circuit 230 or the circuit 240 whilethe potentials of the wiring RW[p] and the wiring RW[p+1] are kept atbase potentials.

Specifically, when the current I[q] is higher than the current IREF, thecircuit 230 supplies the current Ioffset[q] to the wiring BL[q]. Thismeans that a current ICM[q] that flows in the circuit 230 corresponds tothe current Ioffset[q]. The value of the current ICM[q] is held in thecircuit 230. When the current I[q] is lower than the current IREF, thecircuit 240 draws the current Ioffset[q] from the wiring BL[q]. Thismeans that a current ICP [q] that flows in the circuit 240 correspondsto the current Ioffset[q]. The value of the current ICP [q] is held inthe circuit 240.

Then, the second analog potential or a potential corresponding to thesecond analog potential is stored in the memory cell MC[p, q] so as tobe added to the first analog potential or a potential corresponding tothe first analog potential that has been held in the memory cell MC[p,q]. Specifically, when the potential of the wiring RW[p] is set to apotential that is higher than a base potential by Vw[p], a second analogpotential Vw[p] is input to the memory cell MC[p, q] through the wiringRW[p]. The memory cell MC[p, q] holds a potential VPR−Vx[p, q]+Vw[p].Furthermore, the memory cell MC[p, q] generates the current I[p, q]corresponding to the potential VPR−Vx[p, q]+Vw[p].

In addition, the second analog potential or the potential correspondingto the second analog potential is stored in the memory cell MC[p−1, q]so as to be added to the first analog potential or a potentialcorresponding to the first analog potential that has been held in thememory cell MC[p+1, q]. Specifically, when the potential of the wiringRW[p+1] is set to a potential that is higher than a base potential byVw[p+1], a second analog potential Vw[p+1] is input to the memory cellMC[p+1, q] through the wiring RW[p+1]. The memory cell MC[p+1, q] holdsa potential VPR−Vx[p+1, q]+Vw[p+1]. Furthermore, the memory cell MC[p+1,q] generates the current I[p+1, q] corresponding to the potentialVPR−Vx[p+1, q]+Vw[p+1].

In the case where the transistor Tr11 that operates in a saturationregion is used as an element for converting a potential into current,Vw[p] is assumed to be the potential of the wiring RW[p], and Vw[p+1] isassumed to be the potential of the wiring RW[p+1], since the draincurrent of the transistor Tr11 included in the memory cell MC[p, q]corresponds to the current I[p, q], the second analog current isexpressed by Formula 1 below. Note that k is a coefficient and Vth isthe threshold voltage of the transistor Tr11.

I[p,q]=k(Vw[p]−Vth+VPR−Vx[p,q])²  (Formula 1)

Furthermore, since the drain current of the transistor Tr11 included inthe memory cell MCR[p] corresponds to the current IREF[p], the secondreference current is expressed by Formula 2 below.

IREF[p]=k(Vw[p]−Vth+VPR)²  (Formula 2)

The current I[q], which corresponds to the sum of the current I[p, q]flowing in the memory cell MC[p, q] and the current I[p+1, q] flowing inthe memory cell MC[p+1, q], is expressed as ΣiI[p, q], and the currentIREF, which corresponds to the sum of the current IREF[p] flowing in thememory cell MCR[p] and the current IREF[p+1] flowing in the memory cellMCR[p+1], is expressed as ΣiIREF[p]; accordingly, the current ΔI[q] thatcorresponds to the difference between the current I[q] and the currentIREF is expressed by Formula 3 below.

ΔI[q]=IREF−I[q]=ΣiIREF[p]−ΣiI[p,q]  (Formula 3)

The current ΔI[q] can be obtained from Formula 1, Formula 2, and Formula3, as expressed by Formula 4 below.

ΔI[q]=Σi{k(Vw[p]−Vth+VPR)²−k(Vw[p]−Vth+VPR−Vx[p,q])²}=2kΣi(Vw[p]·Vx[p,q])−2kΣi(Vth−VPR)·Vx[p,q]−kΣiVx[p,q]²  Formula4)

The term 2kΣi(Vw[p]·Vx[p, q]) in Formula 4 corresponds to the sum of theproduct of the first analog potential Vx[p, q] and the second analogpotential Vw[p] and the product of the first analog potential Vx[p+1, q]and the second analog potential Vw[p+1].

Furthermore, if the current Ioffset[q] is defined as the current ΔI[q]at the time when the potential of the wiring RW[p] is all set to a basepotential, that is, when the second analog potential Vw[p] is 0 and thesecond analog potential Vw[p+1] is 0, Formula 5 below can be obtainedfrom Formula 4.

Ioffset[q]=−2kτi(Vth−VPR)·Vx[p,q]−kΣiVx[p,q]²  (Formula 5)

According to Formulae 3 to 5, 2kΣi(Vw[p]·Vx[p, q]) that corresponds tothe product-sum of the first analog data and the second analog data isexpressed by Formula 6 below.

2kΣi(Vw[p]·Vx[p,q])=IREF−I[q]−Ioffset[q]  (Formula 6)

When the potential of the wiring RW[p] is Vw[p] and the potential of thewiring RW[p+1] is Vw[p+1], a current Iout[q] that flows from the wiringBL[q] is expressed by IREF−I[q]·Ioffset[q], where I[q] is the sum ofcurrents flowing in the memory cells MC, IREF is the sum of currentsflowing in the memory cells MCR, and Ioffset[q] is current flowing inthe circuit 230 or the circuit 240. According to Formula 6, the currentIout[q] is equal to 2kΣi(Vw[p]·Vx[p, q]), which corresponds to the sumof the product of the first analog potential Vx[p, q] and the secondanalog potential Vw[p] and the product of the first analog potentialVx[p+1, q] and the second analog potential Vw[p+1].

The transistor Tr11 desirably operates in a saturation region; however,even if the operation region of the transistor Tr11 deviates from anideal saturation region, the transistor Tr11 is regarded as operating ina saturation region as long as there is no problem in obtaining currentthat corresponds to the sum of the product of the first analog potentialVx[p, q] and the second analog potential Vw[p] and the product of thefirst analog potential Vx[p+1, q] and the second analog potentialVw[p+1] with an accuracy within a desired range.

According to one embodiment of the present invention, analog data can besubjected to arithmetic processing without being converted into digitaldata; thus, the circuit scale of a semiconductor device can be reduced.Alternatively, according to one embodiment of the present invention,analog data can be subjected to arithmetic processing without beingconverted into digital data; thus, the time required for the arithmeticprocessing of analog data can be shortened. Alternatively, according toone embodiment of the present invention, power consumption of asemiconductor device can be reduced while the time required forarithmetic processing of analog data is shortened.

<Structure Example of Memory Circuit>

Next, a specific structure example of the memory circuit 210 (MEM) andthe reference memory circuit 220 (RMEM) is described with reference toFIG. 13.

FIG. 13 illustrates an example where the memory circuit 210 (MEM)includes the memory cells MC in y rows and x columns (x and y arenatural numbers) and the reference memory circuit 220 (RMEM) includesthe memory cells MCR in y rows and one column.

Note that a source of a transistor in this specification and the likemeans a source region that is part of a semiconductor layer functioningas a channel region, a source electrode connected to the semiconductorlayer, or the like. Similarly, a drain of a transistor means a drainregion that is part of the semiconductor layer, a drain electrodeconnected to the semiconductor layer, or the like. A gate means a gateelectrode or the like.

The names of a source and a drain of a transistor interchange with eachother depending on the conductivity type of the transistor or levels ofpotentials applied to the terminals. In general, in an n-channeltransistor, a terminal to which a lower potential is applied is called asource, and a terminal to which a higher potential is applied is calleda drain. In a p-channel transistor, a terminal to which a lowerpotential is applied is called a drain, and a terminal to which a higherpotential is applied is called a source. In this specification, althoughthe connection relation of a transistor is sometimes described assumingthat the source and the drain are fixed for convenience, actually, thenames of the source and the drain interchange with each other dependingon the relation of the potentials.

The memory circuit 210 is connected to the wiring RW, a wiring WW, thewiring WD, the wiring VR, and the wiring BL. In the example illustratedin FIG. 13, wirings RW[1] to RW[y] are connected to the memory cells MCin the respective rows, wirings WW[1] to WW[y] are connected to thememory cells MC in the respective rows, wirings WD[1] to WD[x] areconnected to the memory cells MC in the respective columns, and wiringsBL[1] to BL[x] are connected to the memory cells MC in the respectivecolumns. Moreover, in the example illustrated in FIG. 13, wirings VR[1]to VR[x] are connected to the memory cells MC in the respective columns.Note that the wirings VR[1] to VR[x] may be connected to each other.

The reference memory circuit 220 is connected to the wiring RW, thewiring WW, the wiring WDREF, the wiring VRREF, and the wiring BLREF. Inthe example illustrated in FIG. 13, the wirings RW[1] to RW[y] areconnected to the memory cells MCR in the respective rows, the wiringsWW[1] to WW[y] are connected to the memory cells MCR in the respectiverows, the wiring WDREF is connected to the memory cells MCR in the onecolumn, the wiring BLREF is connected to the memory cells MCR in the onecolumn, and the wiring VRREF is connected to the memory cells MCR in theone column. Note that the wiring VRREF may be connected to the wiringsVR[1] to VR[x].

Next, FIG. 14 illustrates, as an example, a specific circuit structureand a specific connection relation of the memory cells MC in any tworows and two columns among the memory cells MC illustrated in FIG. 13and the memory cells MCR in any two rows and one column among the memorycells MCR illustrated in FIG. 13.

Specifically, FIG. 14 illustrates the memory cell MC[p, q] in the p-throw and the q-th column, the memory cell MC[p+1, q] in the p+1-th rowand the q-th column, a memory cell MC[p, q+1] in the p-th row and theq+1-th column, and a memory cell MC[p+1, q+1] in the p+1-th row and theq+1-th column. Furthermore, specifically, FIG. 14 illustrates the memorycell MCR[p] in the p-th row and the memory cell MCR[p+1] in the p+1-throw. Note that p is any number from 1 to (y−1), and q is any number from1 to (x−1).

The memory cell MC[p, q], the memory cell MC[p, q+1], and the memorycell MCR[p] in the p-th row are connected to the wiring RW[p] and awiring WW[p]. The memory cell MC[p+1, q], the memory cell MC[p+1, q+1],and the memory cell MCR[p+1] in the p+1-th row are connected to thewiring RW[p+1] and a wiring WW[p+1].

The memory cell MC[p, q] and the memory cell MC[p+1, q] in the q-thcolumn are connected to the wiring WD[q], the wiring VR[q], and thewiring BL[q]. The memory cell MC[p, q+1] and the memory cell MC[p+1,q+1] in the q+1-th column are connected to a wiring WD[q+1], a wiringVR[q+1], and a wiring BL[q+1]. The memory cell MCR[p] in the p-th rowand the memory cell MCR[p+1] in the p+1-th row are connected to thewiring WDREF, the wiring VRREF, and the wiring BLREF.

The memory cells MC and the memory cells MCR each include the transistorTr11, a transistor Tr12, and a capacitor C11. The transistor Tr12 has afunction of controlling the input of the first analog potential to thememory cell MC or the memory cell MCR. The transistor Tr11 has afunction of generating analog current in accordance with a potentialinput to its gate. The capacitor C11 has a function of adding the secondanalog potential or a potential corresponding to the second analogpotential to the first analog potential or a potential corresponding tothe first analog potential that is held in the memory cell MC or thememory cell MCR.

Specifically, in the memory cell MC illustrated in FIG. 14, a gate ofthe transistor Tr12 is connected to the wiring WW, one of a source and adrain is connected to the wiring WD, and the other of the source and thedrain is connected to the gate of the transistor Tr11. Furthermore, oneof the source and the drain of the transistor Tr11 is connected to thewiring VR, and the other of the source and the drain is connected to thewiring BL. A first electrode of the capacitor C11 is connected to thewiring RW, and a second electrode is connected to the gate of thetransistor Till.

In addition, in the memory cell MCR illustrated in FIG. 14, the gate ofthe transistor Tr12 is connected to the wiring WW, one of the source andthe drain is connected to the wiring WDREF, and the other of the sourceand the drain is connected to the gate of the transistor Tr11.Furthermore, one of the source and the drain of the transistor Tr11 isconnected to the wiring VRREF, and the other of the source and the drainis connected to the wiring BLREF. The first electrode of the capacitorC11 is connected to the wiring RW, and the second electrode is connectedto the gate of the transistor Tr11.

When the gate of the transistor Tr11 in the memory cell MC is called anode N, in the memory cell MC, the first analog potential or thepotential corresponding to the first analog potential is input to thenode N through the transistor Tr12, and then, when the transistor Tr12is turned off, the node N is brought into a floating state and the firstanalog potential or the potential corresponding to the first analogpotential is held at the node N. In the memory cell MC, when the node Nis brought into a floating state, the second analog potential or thepotential corresponding to the second analog potential that is input tothe first electrode of the capacitor C11 is applied to the node N. As aresult of the above operation, the node N can have a potential obtainedby adding the second analog potential or the potential corresponding tothe second analog potential to the first analog potential or thepotential corresponding to the first analog potential.

Since the potential of the first electrode of the capacitor C11 isapplied to the node N through the capacitor C11, the amount of change inthe potential of the first electrode is not exactly the same as theamount of change in the potential of the node N, actually. Specifically,the accurate amount of change in the potential of the node N can becalculated in the following manner: a coupling coefficient uniquelydetermined by the capacitance value of the capacitor C11, thecapacitance value of the gate capacitance of the transistor Tr11, andthe capacitance value of parasitic capacitance is multiplied by theamount of change in the potential of the first electrode. In thefollowing description, the amount of change in the potential of thefirst electrode is assumed to be substantially the same as the amount ofchange in the potential of the node N, for easy understanding.

The drain current of the transistor Tr11 is determined by the potentialof the node N. Thus, when the transistor Tr12 is turned off and thus thepotential of the node N is held, the value of the drain current of thetransistor Tr11 is also held. The drain current is affected by the firstanalog potential and the second analog potential.

When the gate of the transistor Tr11 in the memory cell MCR is called anode NREF, in the memory cell MCR, the first reference potential or apotential corresponding to the first reference potential is input to thenode NREF through the transistor Tr12, and then, when the transistorTr12 is turned off, the node NREF is brought into a floating state andthe first reference potential or the potential corresponding to thefirst reference potential is held at the node NREF. In the memory cellMCR, when the node NREF is brought into a floating state, the secondanalog potential or the potential corresponding to the second analogpotential that is input to the first electrode of the capacitor C11 isapplied to the node NREF. As a result of the above operation, the nodeNREF can have a potential obtained by adding the second analog potentialor the potential corresponding to the second analog potential to thefirst reference potential or the potential corresponding to the firstreference potential.

The drain current of the transistor Tr11 is determined by the potentialof the node NREF. Thus, when the transistor Tr12 is turned off and thusthe potential of the node NREF is held, the value of the drain currentof the transistor Tr11 is also held. The drain current is affected bythe first reference potential and the second analog potential.

When the drain current flowing in the transistor Tr11 in the memory cellMC[p, q] is the current I[p, q] and the drain current flowing in thetransistor Tr11 in the memory cell MC[p+1, q] is the current I[p+1, q],the sum of currents supplied to the memory cell MC[p, q] and the memorycell MC[p+1, q] from the wiring BL[q] is the current I[q]. When thedrain current flowing in the transistor Tr11 in the memory cell MC[p,q+1] is a current I[p, q+1] and the drain current flowing in thetransistor Tr11 in the memory cell MC[p+1, q+1] is a current I[p+1,q+1], the sum of currents supplied to the memory cell MC[p, q+1] and thememory cell MC[p+1, q+1] from the wiring BL[q+1] is a current I[q+1].When the drain current flowing in the transistor Tr11 in the memory cellMCR[p] is the current IREF[p] and the drain current flowing in thetransistor Tr11 in the memory cell MCR[p+1] is the current IREF[p+1],the sum of currents supplied to the memory cell MCR[p] and the memorycell MCR[p+1] from the wiring BLREF is the current IREF.

<Structure Example of Circuit 230, Circuit 240, and Current SupplyCircuit>

Next, specific structure examples of the circuit 230, the circuit 240,and the current supply circuit 250 (CREF) are described with referenceto FIG. 15.

FIG. 15 illustrates a structure example of the circuit 230, the circuit240, and the current supply circuit 250 for the memory cells MC and thememory cells MCR illustrated in FIG. 14. Specifically, the circuit 230illustrated in FIG. 15 includes a circuit 230[q] for the memory cells MCin the q-th column and a circuit 230[q+1] for the memory cells MC in theq+1-th column. Furthermore, the circuit 240 illustrated in FIG. 15includes a circuit 240[q] for the memory cells MC in the q-th column anda circuit 240[q+1] for the memory cells MC in the q+1-th column.

The circuit 230[q] and the circuit 240[q] are connected to the wiringBL[q]. The circuit 230[q+1] and the circuit 240[q+1] are connected tothe wiring BL[q+1].

The current supply circuit 250 is connected to the wiring BL[q], thewiring BL[q+1], and the wiring BLREF. The current supply circuit 250 hasa function of supplying the current IREF to the wiring BLREF and afunction of supplying current that is the same as the current IREF orcurrent that corresponds to the current IREF to each of the wiring BL[q]and the wiring BL[q+1].

Specifically, the circuit 230[q] and the circuit 230[q+1] each includetransistors Tr24 to Tr26 and a capacitor C22. The transistor Tr24 in thecircuit 230[q] has a function of generating the current ICM[q] thatcorresponds to the difference between the current I[q] and the currentIREF, when the current I[q] is higher than the current IREF and offsetcurrent is set. Furthermore, the transistor Tr24 in the circuit 230[q+1]has a function of generating a current ICM[q+1] that corresponds to thedifference between the current I[q+1] and the current IREF, when thecurrent I[q+1] is higher than the current IREF. The current ICM[q] andthe current ICM[q+1] are supplied from the circuit 230[q] and thecircuit 230[q+1] to the wiring BL[q] and the wiring BL[q+1],respectively.

In each of the circuit 230[q] and the circuit 230[q+1], one of a sourceand a drain of the transistor Tr24 is connected to the correspondingwiring BL, and the other of the source and the drain is connected to awiring through which a predetermined potential is supplied. One of asource and a drain of the transistor Tr25 is connected to thecorresponding wiring BL, and the other of the source and the drain isconnected to a gate of the transistor Tr24. One of a source and a drainof the transistor Tr26 is connected to the gate of the transistor Tr24,and the other of the source and the drain is connected to a wiringthrough which a predetermined potential is supplied. A first electrodeof the capacitor C22 is connected to the gate of the transistor Tr24,and a second electrode is connected to a wiring through which apredetermined potential is supplied.

A gate of the transistor Tr25 is connected to a wiring OSM, and a gateof the transistor Tr26 is connected to a wiring ORM.

Note that FIG. 15 illustrates an example where the transistor Tr24 is ap-channel transistor and the transistors Tr25 and Tr26 are n-channeltransistors.

The circuit 240[q] and the circuit 240[q+1] each include transistorsTr21 to Tr23 and a capacitor C21. The transistor Tr21 in the circuit240[q] has a function of generating the current ICP[q] that correspondsto the difference between the current I[q] and the current IREF, whenthe current I[q] is lower than the current IREF and offset current isset. Furthermore, the transistor Tr21 in the circuit 240[q+1] has afunction of generating a current ICP[q+1] that corresponds to thedifference between the current I[q+1] and the current IREF, when thecurrent I[q+1] is lower than the current IREF. The current ICP[q] andthe current ICP[q+1] are drawn from the wiring BL[q] and the wiringBL[q+1] into the circuit 240[q] and the circuit 240[q+1], respectively.

Note that the current ICM[q] and the current ICP[q] each correspond tothe current Ioffset[q]. The current ICM[q+1] and the current ICP[q+1]each correspond to a current Ioffset[q+1].

In each of the circuit 240[q] and the circuit 240[q+1], one of a sourceand a drain of the transistor Tr21 is connected to the correspondingwiring BL, and the other of the source and the drain is connected to awiring through which a predetermined potential is supplied. One of asource and a drain of the transistor Tr22 is connected to the wiring BL,and the other of the source and the drain is connected to a gate of thetransistor Tr21. One of a source and a drain of the transistor Tr23 isconnected to the gate of the transistor Tr21, and the other of thesource and the drain is connected to a wiring through which apredetermined potential is supplied. A first electrode of the capacitorC21 is connected to the gate of the transistor Tr21, and a secondelectrode is connected to a wiring through which a predeterminedpotential is supplied.

A gate of the transistor Tr22 is connected to a wiring OSP, and a gateof the transistor Tr23 is connected to a wiring ORP.

Note that FIG. 15 illustrates an example where the transistors Tr21 toTr23 are n-channel transistors.

The current supply circuit 250 includes a transistor Tr27 for the wiringBL and a transistor Tr28 for the wiring BLREF. Specifically, FIG. 15illustrates an example where the current supply circuit 250 includes, asthe transistor Tr27, a transistor Tr27[q] for the wiring BL[q] and atransistor Tr27[q+1] for the wiring BL[q+1].

A gate of the transistor Tr27 is connected to a gate of the transistorTr28. One of a source and a drain of the transistor Tr27 is connected tothe corresponding wiring BL, and the other of the source and the drainis connected to a wiring through which a predetermined potential issupplied. One of a source and a drain of the transistor Tr28 isconnected to the wiring BLREF, and the other of the source and the drainis connected to a wiring through which a predetermined potential issupplied.

The transistor Tr27 and the transistor Tr28 have the same polarity. FIG.15 illustrates an example where the transistor Tr27 and the transistorTr28 are p-channel transistors.

The drain current of the transistor Tr28 corresponds to the currentIREF. The transistor Tr27 and the transistor Tr28 collectively serve asa current mirror circuit; thus, the drain current of the transistor Tr27is substantially the same as the drain current of the transistor Tr28 orcorresponds to the drain current of the transistor Tr28.

<Operation Example of Semiconductor Device>

Next, a specific operation example of the semiconductor device 200 ofone embodiment of the present invention is described with reference toFIG. 14 to FIG. 16.

FIG. 16 corresponds to an example of a timing chart showing theoperations of the memory cells MC and the memory cells MCR illustratedin FIG. 14 and the circuit 230, the circuit 240, and the current supplycircuit 250 illustrated in FIG. 15. From Time T01 to Time T04 in FIG.16, the first analog data is stored in the memory cells MC and thememory cells MCR. From Time T05 to Time T10, the current value of theoffset current Ioffset that is supplied from the circuit 230 and thecircuit 240 is set. From Time T11 to Time T16, data corresponding to theproduct-sum of the first analog data and the second analog data isobtained.

Note that a low-level potential is supplied to the wiring VR[q] and thewiring VR[q+1]. The high-level potential VDD is supplied to all wiringshaving a predetermined potential that are connected to the circuit 230.The low-level potential VSS is supplied to all wirings having apredetermined potential that are connected to the circuit 240.Furthermore, the high-level potential VDD is supplied to all wiringshaving a predetermined potential that are connected to the currentsupply circuit 250.

The transistors Tr11, Tr21, Tr24, Tr27[q], Tr27[q+1], and Tr28 eachoperate in a saturation region.

First, a high-level potential is applied to the wiring WW[p] and alow-level potential is applied to the wiring WW[p+1] from Time T01 toTime T02. As a result of the above operation, the transistors Tr12 inthe memory cell MC[p, q], the memory cell MC[p, q+1], and the memorycell MCR[p] illustrated in FIG. 14 are turned on. The transistors Tr12in the memory cell MC[p+1, q], the memory cell MC[p+1, q+1], and thememory cell MCR[p+1] remain off.

In addition, from Time T01 to Time T02, a potential obtained bysubtracting the first analog potential from the first referencepotential VPR is applied to each of the wiring WD[q] and the wiringWD[q+1] illustrated in FIG. 14. Specifically, the potential VPR−Vx[p, q]is applied to the wiring WD[q], and a potential VPR−Vx[p, q+1] isapplied to the wiring WD[q+1]. The first reference potential VPR isapplied to the wiring WDREF, and a potential between the potential VSSand the potential VDD, e.g., a potential (VDD+VSS)/2, is applied as abase potential to the wiring RW[p] and the wiring RW[p+1].

Accordingly, in FIG. 14, the potential VPR−Vx[p, q] is applied to a nodeN[p, q] through the transistor Tr12 in the memory cell MC[p, q], thepotential VPR−Vx[p, q+1] is applied to a node N[p, q+1] through thetransistor Tr12 in the memory cell MC[p, q+1], and the first referencepotential VPR is applied to a node NREF[p] through the transistor Tr12in the memory cell MCR[p].

After Time T02, the potential applied to the wiring WW[p] illustrated inFIG. 14 changes from a high level to a low level, so that thetransistors Tr12 in the memory cell MC[p, q], the memory cell MC[p,q+1], and the memory cell MCR[p] are turned off. As a result of theabove operation, the potential VPR−Vx[p, q] is held at the node N[p, q],the potential VPR−Vx[p, q+1] is held at the node N[p, q+1], and thefirst reference potential VPR is held at the node NREF[p].

Then, from Time T03 to Time T04, the potential of the wiring WW[p]illustrated in FIG. 14 remains at a low level and a high-level potentialis applied to the wiring WW[p+1]. As a result of the above operation,the transistors Tr12 in the memory cell MC[p+1, q], the memory cellMC[p+1, q+1], and the memory cell MCR[p+1] illustrated in FIG. 14 areturned on. The transistors Tr12 in the memory cell MC[p, q], the memorycell MC[p, q+1], and the memory cell MCR[p] remain off.

In addition, from Time T03 to Time T04, a potential obtained bysubtracting the first analog potential from the first referencepotential VPR is applied to each of the wiring WD[q] and the wiringWD[q+1] illustrated in FIG. 14. Specifically, the potential VPR−Vx[p+1,q] is applied to the wiring WD[q], and a potential VPR−Vx[p+1, q+1] isapplied to the wiring WD[q+1]. The first reference potential VPR isapplied to the wiring WDREF, and a potential between the potential VSSand the potential VDD, e.g., the potential (VDD+VSS)/2, is applied as abase potential to the wiring RW[p] and the wiring RW[p+1].

Accordingly, in FIG. 14, the potential VPR−Vx[p+1, q] is applied to anode N[p+1, q] through the transistor Tr12 in the memory cell MC[p+1,q], the potential VPR−Vx[p+1, q+1] is applied to a node N[p+1, q+1]through the transistor Tr12 in the memory cell MC[p+1, q+1], and thefirst reference potential VPR is applied to a node NREF[p+1] through thetransistor Tr12 in the memory cell MCR[p+1].

After Time T04, the potential applied to the wiring WW[p+1] illustratedin FIG. 14 changes from a high level to a low level, so that thetransistors Tr12 in the memory cell MC[p+1, q], the memory cell MC[p+1,q+1], and the memory cell MCR[p+1] are turned off. As a result of theabove operation, the potential VPR−Vx[p+1, q] is held at the node N[p+1,q], the potential VPR−Vx[p+1, q+1] is held at the node N[p+1, q+1], andthe first reference potential VPR is held at the node NREF[p+1].

Next, a high-level potential is applied to the wiring ORP and the wiringORM illustrated in FIG. 15 from Time T05 to Time T06. When a high-levelpotential is applied to the wiring ORM, the transistors Tr26 in thecircuit 230[q] and the circuit 230[q+1] illustrated in FIG. 15 areturned on, so that the gates of the transistors Tr24 are reset by thepotential VDD applied thereto. Furthermore, when a high-level potentialis applied to the wiring ORP, the transistors Tr23 in the circuit 240[q]and the circuit 240[q+1] illustrated in FIG. 15 are turned on, so thatthe gates of the transistors Tr21 are reset by the potential VSS appliedthereto.

After Time T06, the potential applied to the wiring ORP and the wiringORM illustrated in FIG. 14 changes from a high level to a low level, sothat the transistors Tr26 in the circuit 230[q] and the circuit 230[q+1]are turned off and the transistors Tr23 in the circuit 240[q] and thecircuit 240[q+1] are turned off. As a result of the above operation, thepotential VDD is held at the gate of the transistor Tr24 in each of thecircuit 230[q] and the circuit 230[q+1], and the potential VSS is heldat the gate of the transistor Tr21 in each of the circuit 240[q] and thecircuit 240[q+1].

Next, from Time T07 to Time T08, a high-level potential is applied tothe wiring OSP illustrated in FIG. 15. Furthermore, a potential betweenthe potential VS S and the potential VDD, e.g., the potential(VDD+VSS)/2, is applied as a base potential to the wiring RW[p] and thewiring RW[p+1] illustrated in FIG. 14. Since a high-level potential isapplied to the wiring OSP, the transistors Tr22 in the circuit 240[q]and the circuit 240[q+1] are turned on.

If the current I[q] flowing through the wiring BL[q] is lower than thecurrent IREF flowing through the wiring BLREF, that is, if the currentΔI[q] has a positive value, it means that the sum of current that can bedrawn by the transistor Tr28 in the memory cell MC[p, q] illustrated inFIG. 14 and current that can be drawn by the transistor Tr28 in thememory cell MC[p+1, q] is smaller than the value of the drain current ofthe transistor Tr27[q]. Thus, if the current ΔI[q] has a positive value,part of the drain current of the transistor Tr27[q] flows to the gate ofthe transistor Tr21 when the transistor Tr22 is turned on in the circuit240[q], and the potential of the gate starts to increase. When the draincurrent of the transistor Tr21 becomes substantially equal to thecurrent ΔI[q], the potential of the gate of the transistor Tr21converges on a certain value. The potential of the gate of thetransistor Tr21 at this time corresponds to a potential at which thedrain current of the transistor Tr21 becomes the current ΔI[q], i.e.,the current Ioffset[q] (=ICP[q]). This means that the transistor Tr21 inthe circuit 240[q] is in a state of serving as a current source that cansupply the current ICP[q].

Similarly, if the current I[q+1] flowing through the wiring BL[q+1] islower than the current IREF flowing through the wiring BLREF, that is,if a current ΔI[q+1] has a positive value, part of the drain current ofthe transistor Tr27[q+1] flows to the gate of the transistor Tr21 whenthe transistor Tr22 is turned on in the circuit 240[q+1], and thepotential of the gate starts to increase. When the drain current of thetransistor Tr21 becomes substantially equal to the current ΔI[q+1], thepotential of the gate of the transistor Tr21 converges on a certainvalue. The potential of the gate of the transistor Tr21 at this timecorresponds to a potential at which the drain current of the transistorTr21 becomes the current ΔI[q+1], i.e., the currentIoffset[q+1](=ICP[q+1]). This means that the transistor Tr21 in thecircuit 240[q+1] is in a state of serving as a current source that cansupply the current ICP[q+1].

After Time T08, the potential applied to the wiring OSP illustrated inFIG. 15 changes from a high level to a low level, so that thetransistors Tr22 in the circuit 240[q] and the circuit 240[q+1] areturned off. As a result of the above operation, the potentials of thegates of the transistors Tr21 are held. Thus, the circuit 240[q] remainsin a state of serving as the current source that can supply the currentICP[q], and the circuit 240[q+1] remains in a state of serving as thecurrent source that can supply the current ICP[q+1].

Next, from Time T09 to Time T10, a high-level potential is applied tothe wiring OSM illustrated in FIG. 15. Furthermore, a potential betweenthe potential VS S and the potential VDD, e.g., the potential(VDD+VSS)/2, is applied as a base potential to the wiring RW[p] and thewiring RW[p+1] illustrated in FIG. 14. Since a high-level potential isapplied to the wiring OSM, the transistors Tr25 in the circuit 230[q]and the circuit 230[q+1] are turned on.

If the current I[q] flowing through the wiring BL[q] is higher than thecurrent IREF flowing through the wiring BLREF, that is, if the currentΔI[q] has a negative value, it means that the sum of current that can bedrawn by the transistor Tr28 in the memory cell MC[p, q] illustrated inFIG. 14 and current that can be drawn by the transistor Tr28 in thememory cell MC[p+1, q] is larger than the value of the drain current ofthe transistor Tr27[q]. Thus, if the current ΔI[q] has a negative value,current flows from the gate of the transistor Tr24 to the wiring BL[q]when the transistor Tr25 is turned on in the circuit 230[q], and thepotential of the gate starts to decrease. When the drain current of thetransistor Tr24 becomes substantially equal to the current ΔI[q], thepotential of the gate of the transistor Tr24 converges on a certainvalue. The potential of the gate of the transistor Tr24 at this timecorresponds to a potential at which the drain current of the transistorTr24 becomes the current ΔI[q], i.e., the current Ioffset[q] (=ICM[q]).This means that the transistor Tr24 in the circuit 230[q] is in a stateof serving as a current source that can supply the current ICM[q].

Similarly, if the current I[q+1] flowing through the wiring BL[q+1] ishigher than the current IREF flowing through the wiring BLREF, that is,if the current ΔI[q+1] has a negative value, current flows from the gateof the transistor Tr24 in the circuit 230[q+1] to the wiring BL[q+1]when the transistor Tr25 is turned on, and the potential of the gatestarts to decrease. When the drain current of the transistor Tr24becomes substantially equal to the absolute value of the currentΔI[q+1], the potential of the gate of the transistor Tr24 converges on acertain value. The potential of the gate of the transistor Tr24 at thistime corresponds to a potential at which the drain current of thetransistor Tr24 becomes equal to the absolute value of the currentΔI[q+1], i.e., the current Ioffset[q+1] (=ICM[q+1]). This means that thetransistor Tr24 in the circuit 230[q+1] is in a state of serving as acurrent source that can supply the current ICM[q+1].

After Time T08, the potential applied to the wiring OSM illustrated inFIG. 15 changes from a high level to a low level, so that thetransistors Tr25 in the circuit 230[q] and the circuit 230[q+1] areturned off. As a result of the above operation, the potentials of thegates of the transistors Tr24 are held. Thus, the circuit 230[q] remainsin a state of serving as the current source that can supply the currentICM[q], and the circuit 230[q+1] remains in a state of serving as thecurrent source that can supply the current ICM[q+1].

In each of the circuit 240[q] and the circuit 240[q+1], the transistorTr21 has a function of drawing current. Thus, from Time T07 to Time T08,when the current I[q] flowing through the wiring BL[q] is higher thanthe current IREF flowing through the wiring BLREF and the current ΔI[q]has a negative value, or when the current I[q+1] flowing through thewiring BL[q+1] is higher than the current IREF flowing through thewiring BLREF and the current ΔI[q+1] has a negative value, it might bedifficult to supply current from the circuit 240[q] or the circuit 240[q+1] to the wiring BL[q] or the wiring BL[q+1] without excess ordeficiency. In that case, it might be difficult for the transistor Tr11in the memory cell MC, the transistor Tr21 in the circuit 240[q] or thecircuit 240[q+1], and the transistor Tr27[q] or Tr27[q+1] toconcurrently operate in a saturation region because a balance betweenthe current flowing through the wiring BLREF and the current flowingthrough the wiring BL[q] or the wiring BL[q+1] is struck.

To ensure the operations of the transistors Tr11, Tr21, and Tr27[q] orTr27[q+1] in a saturation region from Time T07 to Time T08 even when thecurrent ΔI[q] has a negative value, the potential of the gate of thetransistor Tr24 may be set to a potential that is high enough to obtaina predetermined drain current, instead of resetting the potential of thegate of the transistor Tr24 to the potential VDD, from Time T05 to TimeT06. In the above structure, the amount of current that cannot be drawnby the transistor Tr11 can be drawn by the transistor Tr21 to someextent because current from the transistor Tr24, as well as the draincurrent of the transistor Tr27[q] or Tr27[q+1], is supplied; thus, theoperations of the transistors Tr11, Tr21, and Tr27[q] or Tr27[q+1] in asaturation region can be ensured.

Note that if the current I[q] flowing through the wiring BL[q] is lowerthan the current IREF flowing through the wiring BLREF, that is, if thecurrent ΔI[q] has a positive value, from Time T09 to Time T10, since thecircuit 240[q] has been set as the current source that can supply thecurrent ICP[q] from Time T07 to Time T08, the potential of the gate ofthe transistor Tr24 in the circuit 230[q] remains substantially the sameas the potential VDD. Similarly, if the current I[q+1] flowing throughthe wiring BL[q+1] is lower than the current IREF flowing through thewiring BLREF, that is, if the current ΔI[q+1] has a positive value,since the circuit 240[q+1] has been set as the current source that cansupply the current ICP[q+1] from Time T07 to Time T08, the potential ofthe gate of the transistor Tr24 in the circuit 230[q+1] remainssubstantially the same as the potential VDD.

Then, from Time T11 to Time T12, the second analog potential Vw[p] isapplied to the wiring RW[p] illustrated in FIG. 14. Furthermore, apotential between the potential VSS and the potential VDD, e.g., thepotential (VDD+VSS)/2, is still applied as a base potential to thewiring RW[p+1]. Specifically, the potential of the wiring RW[p] is apotential higher than the potential between the potential VSS and thepotential VDD (e.g., the potential (VDD+VSS)/2), which is a basepotential, by the potential difference Vw[p]; for the simplicity of thefollowing description, however, the potential of the wiring RW[p] isassumed to be the second analog potential Vw[p].

When the potential of the wiring RW[p] becomes the second analogpotential Vw[p], with the assumption that the amount of change in thepotential of the first electrode of the capacitor C11 is substantiallythe same as the amount of change in the potential of the node N, thepotential of the node N in the memory cell MC[p, q] illustrated in FIG.14 becomes VPR−Vx[p, q]+Vw[p] and the potential of the node N in thememory cell MC[p, q+1] becomes VPR−Vx[p, q+1]+Vw[p]. According toFormula 6 above, the product-sum of the first analog data and the secondanalog data for the memory cell MC[p, q] affects current obtained bysubtracting the current Ioffset[q] from the current ΔI[q], that is, thecurrent Iout[q] flowing from the wiring BL[q]. Furthermore, theproduct-sum of the first analog data and the second analog data for thememory cell MC[p, q+1] affects current obtained by subtracting thecurrent Ioffset[q+1] from the current ΔI[q+1], that is, a currentIout[q+1] flowing from the wiring BL[q+1].

After Time T12, a potential between the potential VSS and the potentialVDD (e.g., the potential (VDD+VSS)/2), which is a base potential, isapplied again to the wiring RW[p].

Then, from Time T13 to Time T14, the second analog potential Vw[p+1] isapplied to the wiring RW[p+1] illustrated in FIG. 14. Furthermore, apotential between the potential VSS and the potential VDD, e.g., thepotential (VDD+VSS)/2, is still applied as a base potential to thewiring RW[p]. Specifically, the potential of the wiring RW[p+1] is apotential higher than the potential between the potential VSS and thepotential VDD (e.g., the potential (VDD+VSS)/2), which is a basepotential, by the potential difference Vw[p+1]; for the simplicity ofthe following description, however, the potential of the wiring RW[p+1]is assumed to be the second analog potential Vw[p+1].

When the potential of the wiring RW[p+1] becomes the second analogpotential Vw[p+1], with the assumption that the amount of change in thepotential of the first electrode of the capacitor C11 is substantiallythe same as the amount of change in the potential of the node N, thepotential of the node N in the memory cell MC[p+1, q] illustrated inFIG. 14 becomes VPR−Vx[p+1, q]+Vw[p+1] and the potential of the node Nin the memory cell MC[p+1, q+1] becomes VPR−Vx[p+1, q+1]+Vw[p+1].According to Formula 6 above, the product-sum of the first analog dataand the second analog data for the memory cell MC[p+1, q] affectscurrent obtained by subtracting the current Ioffset[q] from the currentΔI[q], that is, the current Iout[q]. Furthermore, the product-sum of thefirst analog data and the second analog data for the memory cell MC[p+1,q+1] affects current obtained by subtracting the current Ioffset[q+1]from the current ΔI[q+1], that is, the current Iout[q+1].

After Time T12, a potential between the potential VSS and the potentialVDD (e.g., the potential (VDD+VSS)/2), which is a base potential, isapplied again to the wiring RW[p+1].

Then, from Time T15 to Time T16, the second analog potential Vw[p] isapplied to the wiring RW[p] illustrated in FIG. 14 and the second analogpotential Vw[p+1] is applied to the wiring RW[p+1]. Specifically, thepotential of the wiring RW[p] is a potential higher than the potentialbetween the potential VSS and the potential VDD (e.g., the potential(VDD+VSS)/2), which is a base potential, by the potential differenceVw[p], and the potential of the wiring RW[p+1] is a potential higherthan the potential between the potential VSS and the potential VDD(e.g., the potential (VDD+VSS)/2), which is a base potential, by thepotential difference Vw[p+1]; for the simplicity of the followingdescription, however, the potential of the wiring RW[p] is assumed to bethe second analog potential Vw[p] and the potential of the wiringRW[p+1] is assumed to be the second analog potential Vw[p+1].

When the potential of the wiring RW[p] becomes the second analogpotential Vw[p], with the assumption that the amount of change in thepotential of the first electrode of the capacitor C11 is substantiallythe same as the amount of change in the potential of the node N, thepotential of the node N in the memory cell MC[p, q] illustrated in FIG.14 becomes VPR−Vx[p, q]+Vw[p] and the potential of the node N in thememory cell MC[p, q+1] becomes VPR−Vx[p, q+1]+Vw[p]. Furthermore, whenthe potential of the wiring RW[p+1] becomes the second analog potentialVw[p+1], with the assumption that the amount of change in the potentialof the first electrode of the capacitor C11 is substantially the same asthe amount of change in the potential of the node N, the potential ofthe node N in the memory cell MC[p+1, q] illustrated in FIG. 14 becomesVPR−Vx[p+1, q]+Vw[p+1] and the potential of the node N in the memorycell MC[p+1, q+1] becomes VPR−Vx[p+1, q+1]+Vw[p+1].

According to Formula 6 above, the product-sum of the first analog dataand the second analog data for the memory cell MC[p, q] and the memorycell MC[p+1, q] affects current obtained by subtracting the currentIoffset[q] from the current ΔI[q], that is, the current Iout[q].Furthermore, the product-sum of the first analog data and the secondanalog data for the memory cell MC[p, q+1] and the memory cell MC[p+1,q+1] affects current obtained by subtracting the current Ioffset[q+1]from the current ΔI[q+1], that is, the current Iout[q+1].

After Time T16, a potential between the potential VSS and the potentialVDD (e.g., the potential (VDD+VSS)/2), which is a base potential, isapplied again to the wiring RW[p] and the wiring RW[p+1].

With the above structure, the product-sum operation can be performedwith a small circuit scale. With the above structure, the product-sumoperation can be performed at high speed. With the above structure, theproduct-sum operation can be performed with low power.

Note that a transistor with an extremely low off-state current isdesirably used as the transistor Tr12, Tr22, Tr23, Tr25, or Tr26. When atransistor with an extremely low off-state current is used as thetransistor Tr12, the potential of the node N can be held for a longtime. When a transistor with an extremely low off-state current is usedas the transistors Tr22 and Tr23, the potential of the gate of thetransistor Tr21 can be held for a long time. When a transistor with anextremely low off-state current is used as the transistors Tr25 andTr26, the potential of the gate of the transistor Tr24 can be held for along time.

As a transistor with an extremely low off-state current, an OStransistor may be used. The leakage current of an OS transistornormalized by channel width can be lower than or equal to 10×10⁻²¹ A/μm(10 zA/μm) with a source-drain voltage of 10 V at room temperature(approximately 25° C.).

With the use of the semiconductor device described above, theproduct-sum operation in the neural network NN1 can be performed.

This embodiment can be combined with the description of the otherembodiments as appropriate.

Embodiment 4

In this embodiment, a structure example of an OS transistor that can beused in the above embodiment is described.

<Structure Example of Transistor>

FIG. 17(A) is a top view illustrating a structure example of atransistor. FIG. 17(B) is a cross-sectional view along the line X1-X2 inFIG. 17(A), and FIG. 17(C) is a cross-sectional view along the lineY1-Y2. Here, in some cases, the direction of the line X1-X2 is referredto as a channel length direction and the direction of the line Y1-Y2 asa channel width direction. FIG. 17(B) is a diagram illustrating across-sectional structure of the transistor in the channel lengthdirection, and FIG. 17(C) is a diagram illustrating a cross-sectionalstructure of the transistor in the channel width direction. Note that toclarify the device structure, some components are omitted in FIG. 17(A).

The semiconductor device of one embodiment of the present inventionincludes insulating layers 812 to 820, metal oxide films 821 to 824, andconductive layers 850 to 853. A transistor 801 is formed on aninsulating surface. FIG. 17 illustrates the case where the transistor801 is formed over an insulating layer 811. The transistor 801 iscovered with the insulating layer 818 and the insulating layer 819.

Note that the insulating layers, the metal oxide films, the conductivelayers, and the like that constitute the transistor 801 may be a singlelayer or may be a stack including a plurality of films. They can beformed by a variety of deposition methods such as a sputtering method, amolecular beam epitaxy method (MBE method), a pulsed laser ablationmethod (PLA method), a CVD method, and an atomic layer deposition method(ALD method). Note that examples of a CVD method include a plasma CVDmethod, a thermal CVD method, and a metal organic CVD method.

The conductive layer 850 includes a region that functions as a gateelectrode of the transistor 801. The conductive layer 851 and theconductive layer 852 include regions that function as a source electrodeand a drain electrode. The conductive layer 853 includes a region thatfunctions as a back gate electrode. The insulating layer 817 includes aregion that functions as a gate insulating layer on the gate electrode(front gate electrode) side, and an insulating layer formed of a stackof the insulating layers 814 to 816 includes a region that functions asa gate insulating layer on the back gate electrode side. The insulatinglayer 818 functions as an interlayer insulating layer. The insulatinglayer 819 functions as a barrier layer.

The metal oxide films 821 to 824 are collectively referred to as anoxide layer 830. As illustrated in FIG. 17(B) and FIG. 17(C), the oxidelayer 830 includes a region where the metal oxide film 821, the metaloxide film 822, and the metal oxide film 824 are stacked in this order.In addition, a pair of metal oxide films 823 are positioned over theconductive layer 851 and the conductive layer 852. When the transistor801 is on, a channel formation region is mainly formed in the metaloxide film 822 of the oxide layer 830.

The metal oxide film 824 covers the metal oxide films 821 to 823, theconductive layer 851, and the conductive layer 852. The insulating layer817 is positioned between the metal oxide film 823 and the conductivelayer 850. The conductive layer 851 and the conductive layer 852 eachinclude a region that overlaps with the conductive layer 850 with themetal oxide film 823, the metal oxide film 824, and the insulating layer817 therebetween.

The conductive layer 851 and the conductive layer 852 are formed from ahard mask for forming the metal oxide film 821 and the metal oxide film822. Thus, the conductive layer 851 and the conductive layer 852 do notinclude a region that is in contact with the side surfaces of the metaloxide film 821 and the metal oxide film 822. For example, the metaloxide films 821 and 822, the conductive layer 851, and the conductivelayer 852 can be formed through the following steps. First, a conductivefilm is formed over two stacked metal oxide films. This conductive filmis processed (etched) into a desired shape so that a hard mask isformed. With the use of the hard mask, the shapes of the two metal oxidefilms are processed so that the metal oxide film 821 and the metal oxidefilm 822 that are stacked are formed. Next, the hard mask is processedinto a desired shape so that the conductive layer 851 and the conductivelayer 852 are formed.

Examples of insulating materials used for the insulating layers 811 to818 include aluminum nitride, aluminum oxide, aluminum nitride oxide,aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide,silicon nitride oxide, silicon oxynitride, gallium oxide, germaniumoxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide,hafnium oxide, tantalum oxide, and aluminum silicate. The insulatinglayers 811 to 818 are formed of a single layer or a stack containingthese insulating materials. The layers forming the insulating layers 811to 818 may contain a plurality of insulating materials.

Note that in this specification and the like, oxynitride refers to acompound in which the oxygen content is higher than the nitrogencontent, and nitride oxide refers to a compound in which the nitrogencontent is higher than the oxygen content.

In order to suppress an increase in oxygen vacancies in the oxide layer830, the insulating layers 816 to 818 are preferably insulating layerscontaining oxygen. Further preferably, the insulating layers 816 to 818are formed of an insulating film from which oxygen is released byheating (hereinafter, also referred to as an “insulating film containingexcess oxygen”). Supplying oxygen from the insulating film containingexcess oxygen to the oxide layer 830 can compensate for the oxygenvacancies in the oxide layer 830. The reliability and electricalcharacteristics of the transistor 801 can be improved.

The insulating film containing excess oxygen is a film from which oxygenmolecules at more than or equal to 1.0×10¹⁸ [molecules/cm³] are releasedin TDS (Thermal Desorption Spectroscopy) at a film surface temperatureof higher than or equal to 100° C. and lower than or equal to 700° C.,or higher than or equal to 100° C. and lower than or equal to 500° C.Note that the number of released oxygen molecules is preferably 3.0×10²⁰molecules/cm³ or more.

The insulating film containing excess oxygen can be formed by performingtreatment for adding oxygen to an insulating film. Examples of thetreatment for adding oxygen include heat treatment under an oxygenatmosphere, plasma treatment, and treatment using an ion implantationmethod, an ion doping method, or a plasma immersion ion implantationmethod. As a gas for adding oxygen, an oxygen gas of ¹⁶O₂, ¹⁸O₂, or thelike, a nitrous oxide gas, an ozone gas, or the like can be used.

The hydrogen concentrations of the insulating layers 812 to 819 arepreferably reduced in order to prevent an increase in hydrogenconcentration of the oxide layer 830. In particular, the hydrogenconcentrations of the insulating layers 813 to 818 are preferablyreduced. Specifically, the hydrogen concentrations are lower than orequal to 2×10²⁰ atoms/cm³, preferably lower than or equal to 5×10¹⁹atoms/cm³, further preferably lower than or equal to 1×10¹⁹ atoms/cm³,still further preferably lower than or equal to 5×10¹⁸ atoms/cm³.

The above-mentioned hydrogen concentrations are values measured bysecondary ion mass spectrometry (SIMS).

The transistor 801 preferably has a structure in which the oxide layer830 is surrounded by an insulating layer with oxygen and hydrogenbarrier properties (hereinafter, also referred to as a barrier layer).Employing such a structure can prevent release of oxygen from the oxidelayer 830 and entry of hydrogen into the oxide layer 830. Thereliability and electrical characteristics of the transistor 801 can beimproved.

For example, the insulating layer 819 functions as a barrier layer andat least one of the insulating layers 811, 812, and 814 functions as abarrier layer. The barrier layer can be formed of a material such asaluminum oxide, aluminum oxynitride, gallium oxide, gallium oxynitride,yttrium oxide, yttrium oxynitride, hafnium oxide, hafnium oxynitride, orsilicon nitride.

A structure example of the insulating layers 811 to 818 is described. Inthis example, each of the insulating layers 811, 812, 815, and 819functions as a barrier layer. The insulating layers 816 to 818 are oxidelayers containing excess oxygen. The insulating layer 811 is siliconnitride, the insulating layer 812 is aluminum oxide, and the insulatinglayer 813 is silicon oxynitride. The insulating layers 814 to 816 thatfunction as the gate insulating layer on the back gate electrode sideare a stack of silicon oxide, aluminum oxide, and silicon oxide. Theinsulating layer 817 that functions as the gate insulating layer on thefront gate side is silicon oxynitride. The insulating layer 818 thatfunctions as the interlayer insulating layer is silicon oxide. Theinsulating layer 819 is aluminum oxide.

Examples of conductive materials used for the conductive layers 850 to853 include a metal such as molybdenum, titanium, tantalum, tungsten,aluminum, copper, chromium, neodymium, and scandium; and a metal nitridecontaining the above metal as its component (tantalum nitride, titaniumnitride, molybdenum nitride, and tungsten nitride). It is possible touse a conductive material such as indium tin oxide, indium oxidecontaining tungsten oxide, indium zinc oxide containing tungsten oxide,indium oxide containing titanium oxide, indium tin oxide containingtitanium oxide, indium zinc oxide, or indium tin oxide to which siliconoxide is added.

A structure example of the conductive layers 850 to 853 is described.The conductive layer 850 is a single layer of tantalum nitride ortungsten. Alternatively, the conductive layer 850 is a stack of tantalumnitride, tantalum, and tantalum nitride. The conductive layer 851 is asingle layer of tantalum nitride or a stack of tantalum nitride andtungsten. The structure of the conductive layer 852 is the same as thatof the conductive layer 851. The conductive layer 853 is a single layerof tantalum nitride or a stack of tantalum nitride and tungsten.

In order to reduce the off-state current of the transistor 801, theenergy gap of the metal oxide film 822 is preferably large, for example.The energy gap of the metal oxide film 822 is greater than or equal to2.5 eV and less than or equal to 4.2 eV, preferably greater than orequal to 2.8 eV and less than or equal to 3.8 eV, further preferablygreater than or equal to 3 eV and less than or equal to 3.5 eV.

The oxide layer 830 preferably exhibits crystallinity. At least themetal oxide film 822 preferably exhibits crystallinity. With theabove-described structure, the transistor 801 having favorablereliability and electrical characteristics can be achieved.

Examples of the oxide that can be used for the metal oxide film 822include an In—Ga oxide, an In—Zn oxide, and an In—M-Zn oxide (M is Al,Ga, Y, or Sn). The metal oxide film 822 is not limited to an oxide layercontaining indium. The metal oxide film 822 can be formed using a Zn—Snoxide, a Ga—Sn oxide, or a Zn—Mg oxide, for example. The metal oxidefilms 821, 823, and 824 can also be formed using an oxide that issimilar to that used for the metal oxide film 822. In particular, eachof the metal oxide films 821, 823, and 824 can be formed using a Gaoxide.

When an interface state is formed at the interface between the metaloxide film 822 and the metal oxide film 821, a channel formation regionis formed also in a region in the vicinity of the interface, whichcauses a change in threshold voltage of the transistor 801. It istherefore preferred that the metal oxide film 821 contain at least oneof the metal elements contained in the metal oxide film 822 as itscomponent. Accordingly, an interface state is less likely to be formedat the interface between the metal oxide film 822 and the metal oxidefilm 821, and variations in electrical characteristics such as thresholdvoltage of the transistor 801 can be reduced.

The metal oxide film 824 preferably contains at least one of the metalelements contained in the metal oxide film 822 as its component. Thus,interface scattering is less likely to occur at the interface betweenthe metal oxide film 822 and the metal oxide film 824, and carriertransfer is less likely to be inhibited; hence, the field-effectmobility of the transistor 801 can be increased.

It is preferred that the metal oxide film 822 have the highest carriermobility among the metal oxide films 821 to 824. Accordingly, a channelcan be formed in the metal oxide film 822 that is provided in a positionapart from the insulating layers 816 and 817.

For example, in a metal oxide containing In, such as an In-M-Zn oxide,carrier mobility can be increased by an increase in the In content. Inthe In-M-Zn oxide, the s orbital of heavy metal mainly contributes tocarrier transfer, and a larger number of s orbitals overlap byincreasing the indium content; thus, an oxide having a high indiumcontent has higher mobility than an oxide having a low indium content.Consequently, with the use of an oxide having a high indium content forthe metal oxide film, carrier mobility can be increased.

For this reason, for example, the metal oxide film 822 is formed usingan In—Ga—Zn oxide, and the metal oxide films 821 and 823 are formedusing a Ga oxide. For example, when the metal oxide films 821 to 823 areformed using an In-M-Zn oxide, the In content of the metal oxide film822 is made higher than the In content of the metal oxide films 821 and823. When the In-M-Zn oxide is formed by a sputtering method, the Incontent can be changed by changing the atomic ratio of the metalelements of a target.

For example, the atomic ratio In:M:Zn of the metal elements of a targetused for forming the metal oxide film 822 is preferably 1:1:1, 3:1:2, or4:2:4.1. For example, the atomic ratio In:M:Zn of the metal elements ofa target used for forming the metal oxide films 821 and 823 ispreferably 1:3:2 or 1:3:4. The atomic ratio of an In-M-Zn oxide formedusing a target of In:M:Zn=4:2:4.1 is approximately In:M:Zn=4:2:3.

In order to provide the transistor 801 with stable electricalcharacteristics, it is preferable to reduce the concentration ofimpurities in the oxide layer 830. In the metal oxide, hydrogen,nitrogen, carbon, silicon, and a metal element other than its maincomponent are impurities. For example, hydrogen and nitrogen contributeto formation of donor states, thereby increasing the carrier density. Inaddition, silicon and carbon contribute to formation of impurity statesin the metal oxide. The impurity states serve as traps and might causethe electrical characteristics of the transistor to deteriorate.

For example, the oxide layer 830 includes a region where the siliconconcentration is lower than or equal to 2×10¹⁸ atoms/cm³, preferablylower than or equal to 2×10¹⁷ atoms/cm³. The same applies to the carbonconcentration of the oxide layer 830.

The oxide layer 830 includes a region where the concentration of analkali metal is lower than or equal to 1×10¹⁸ atoms/cm³, preferablylower than or equal to 2×10¹⁶ atoms/cm³. The same applies to theconcentration of an alkaline earth metal in the oxide layer 830.

The oxide layer 830 includes a region where the hydrogen concentrationis lower than 1×10²⁰ atoms/cm³, preferably lower than 1×10¹⁹ atoms/cm³,further preferably lower than 5×10¹⁸ atoms/cm³, still further preferablylower than 1×10¹⁸ atoms/cm³.

The above-mentioned concentrations of the impurities in the oxide layer830 are values obtained by SIMS.

In the case where the metal oxide film 822 contains oxygen vacancies,donor states are sometimes formed by entry of hydrogen into sites ofoxygen vacancies. As a result, the oxygen vacancies become a factor indecreasing the on-state current of the transistor 801. Note that sitesof oxygen vacancies become more stable by entry of oxygen than by entryof hydrogen. Thus, by reducing oxygen vacancies in the metal oxide film822, the on-state current of the transistor 801 can be increased in somecases. Consequently, preventing entry of hydrogen into sites of oxygenvacancies by reducing hydrogen in the metal oxide film 822 is effectivefor on-state current characteristics.

Hydrogen contained in a metal oxide reacts with oxygen bonded to a metalatom to be water, and thus forms an oxygen vacancy in some cases. Entryof hydrogen into the oxygen vacancy sometimes generates an electronserving as a carrier. Furthermore, in some cases, bonding of part ofhydrogen to oxygen bonded to a metal atom generates an electron servingas a carrier. Since the channel formation region is provided in themetal oxide film 822, when hydrogen is contained in the metal oxide film822, the transistor 801 is likely to have normally-on characteristics.Accordingly, it is preferred that hydrogen in the metal oxide film 822be reduced as much as possible.

Note that the metal oxide film 822 may have an n-type region 822 n in aregion in contact with the conductive layer 851 or the conductive layer852. The region 822 n is formed by a phenomenon in which oxygen in themetal oxide film 822 is extracted by the conductive layer 851 or theconductive layer 852, a phenomenon in which a conductive material in theconductive layer 851 or the conductive layer 852 is combined with anelement in the metal oxide film 822, or the like. When the region 822 nis formed, the contact resistance between the conductive layer 851 orthe conductive layer 852 and the metal oxide film 822 can be reduced.

FIG. 17 illustrates an example where the oxide layer 830 has afour-layer structure; however, one embodiment of the present inventionis not limited to this. For example, the oxide layer 830 can have athree-layer structure without the metal oxide film 821 or the metaloxide film 823. Alternatively, one or a plurality of metal oxide filmsthat are similar to the metal oxide films 821 to 824 can be provided atany two or more of the following positions: between given layers in theoxide layer 830, over the oxide layer 830, and under the oxide layer830.

Effects obtained from the stack of the metal oxide films 821, 822, and824 are described with reference to FIG. 18. FIG. 18 is a schematicdiagram of the energy band structure of the channel formation region inthe transistor 801.

In FIG. 18, Ec816 e, Ec821 e, Ec822 e, Ec824 e, and Ec817 e indicate theenergy of the conduction band minimums of the insulating layer 816, themetal oxide film 821, the metal oxide film 822, the metal oxide film824, and the insulating layer 817, respectively.

Here, the energy difference between the vacuum level and the conductionband minimum (also referred to as “electron affinity”) is a valueobtained by subtracting an energy gap from the energy difference betweenthe vacuum level and the valence band maximum (also referred to as anionization potential). Note that the energy gap can be measured using aspectroscopic ellipsometer (UT-300, HORIBA JOBIN YVON S.A.S.). Moreover,the energy difference between the vacuum level and the valence bandmaximum can be measured using an ultraviolet photoelectron spectroscopy(UPS) device (VersaProbe, ULVAC-PHI, Inc.).

Since the insulating layers 816 and 817 are insulators, Ec816 e andEc817 e are closer to the vacuum level than Ec821 e, Ec822 e, and Ec824e (the insulating layers 816 and 817 have low electron affinities).

The metal oxide film 822 has a higher electron affinity than the metaloxide films 821 and 824. For example, the difference in electronaffinity between the metal oxide film 822 and the metal oxide film 821and the difference in electron affinity between the metal oxide film 822and the metal oxide film 824 are each greater than or equal to 0.07 eVand less than or equal to 1.3 eV. The differences in electron affinityare preferably greater than or equal to 0.1 eV and less than or equal to0.7 eV, further preferably greater than or equal to 0.15 eV and lessthan or equal to 0.4 eV. Note that the electron affinity is an energydifference between the vacuum level and the conduction band minimum.

When voltage is applied to the gate electrode (the conductive layer 850)of the transistor 801, a channel is mainly formed in the metal oxidefilm 822 having the highest electron affinity among the metal oxide film821, the metal oxide film 822, and the metal oxide film 824.

An indium gallium oxide has a low electron affinity and a highoxygen-blocking property. Therefore, the metal oxide film 824 preferablycontains an indium gallium oxide. The gallium atomic ratio [Ga/(In+Ga)]is, for example, higher than or equal to 70%, preferably higher than orequal to 80%, further preferably higher than or equal to 90%.

A mixed region of the metal oxide film 821 and the metal oxide film 822sometimes exists between the metal oxide film 821 and the metal oxidefilm 822. Moreover, a mixed region of the metal oxide film 824 and themetal oxide film 822 sometimes exists between the metal oxide film 824and the metal oxide film 822. Because the mixed regions have a lowerinterface state density, a region in which the metal oxide films 821,822, and 824 are stacked has a band structure where the energy in thevicinity of each interface is changed continuously (also referred to ascontinuous j unction).

Electrons transfer mainly through the metal oxide film 822 in the oxidelayer 830 having such an energy band structure. Thus, even when a stateexists at the interface between the metal oxide film 821 and theinsulating layer 816 or at the interface between the metal oxide film824 and the insulating layer 817, electron transfer in the oxide layer830 is less likely to be inhibited by these interface states; hence, theon-state current of the transistor 801 can be increased.

In addition, as shown in FIG. 18, trap states Et826 e and Et827 e due toimpurities or defects might be formed in the vicinity of the interfacebetween the metal oxide film 821 and the insulating layer 816 and thevicinity of the interface between the metal oxide film 824 and theinsulating layer 817, respectively; however, the metal oxide film 822can be made apart from the trap states Et826 e and Et827 e owing to theexistence of the metal oxide films 821 and 824.

Note that when the difference between Ec821 e and Ec822 e is small, anelectron in the metal oxide film 822 might reach the trap state Et826 eby passing over the energy difference. When the electron is trapped atthe trap state Et826 e, negative fixed charge is generated at theinterface with the insulating film, causing the threshold voltage of thetransistor to be shifted in the positive direction. The same applies tothe case where the energy difference between Ec822 e and Ec824 e issmall.

In order to reduce a change in threshold voltage of the transistor 801and make the electrical characteristics of the transistor 801 favorable,the difference between Ec821 e and Ec822 e and the difference betweenEc824 e and Ec822 e are each preferably greater than or equal to 0.1 eV,further preferably greater than or equal to 0.15 eV.

Note that the transistor 801 can alternatively have a structure withouta back gate electrode.

<Example of Stacked-Layer Structure>

Next, a structure of a semiconductor device including a stack of an OStransistor and another transistor is described.

FIG. 19 illustrates an example of a stacked-layer structure of asemiconductor device 860 in which a transistor Tr100 that is a Sitransistor, a transistor Tr200 that is an OS transistor, and a capacitorC100 are stacked.

The semiconductor device 860 includes a stack of a CMOS layer 871,wiring layers W₁ to W5, a transistor layer 872, and wiring layers W6 andW7.

The transistor Tr100 is provided in the CMOS layer 871. A channelformation region of the transistor Tr100 is provided in a single crystalsilicon wafer 870. A gate electrode 873 of the transistor Tr100 isconnected to one electrode 875 of the capacitor C100 through the wiringlayers W₁ to W₅.

The transistor Tr200 is provided in the transistor layer 872. In FIG.19, the transistor Tr200 has a structure similar to that of thetransistor 801 (FIG. 17). An electrode 874 corresponding to one of asource and a drain of the transistor Tr200 is connected to the oneelectrode 875 of the capacitor C100. Note that FIG. 19 illustrates thecase where the transistor Tr200 includes its back gate electrode in thewiring layer W₅. The capacitor C100 is formed in the wiring layer W₆.

The OS transistor and other elements are stacked in the above manner,whereby the circuit area can be reduced.

The above-described structure can be used for the semiconductor device200 described in Embodiment 3 or the like. For example, the transistorTr100, the transistor Tr200, and the capacitor C100 can be used as thetransistor Tr11, the transistor Tr12, and the capacitor C11 in FIG. 14,respectively. It is also possible to use the transistor Tr100, thetransistor Tr200, and the capacitor C100 as the transistor Tr21 or Tr24,the transistor Tr22, Tr23, Tr25, or Tr26, and the capacitor C21 or C22in FIG. 15, respectively.

This embodiment can be combined with the description of the otherembodiments as appropriate.

Embodiment 5

In this embodiment, a structure example of a display device that can beused for the display unit described in the above embodiment isdescribed.

<Structure Example 1 of Display Device>

FIG. 20(A) illustrates a structure example of a display device 400 thatcan be used for the display unit 20. The display device 400 includes apixel unit 401, a driver circuit 402, and a driver circuit 403.

The pixel unit 401 includes a plurality of pixels pix and corresponds tothe display region DSP in FIG. 1. The pixels pix are connected towirings SL and wirings GL. The wirings GL are each connected to thedriver circuit 402, and the wirings SL are connected to the drivercircuit 403. Selection signals are supplied to the wirings GL, and imagesignals are supplied to the wirings SL.

The driver circuit 402 has a function of supplying selection signals tothe pixels pix. Specifically, the driver circuit 402 has a function ofsupplying selection signals to the wirings GL, and the wirings GL have afunction of transmitting the selection signals output from the drivercircuit 402 to the pixels pix. Note that the driver circuit 402 can bereferred to as a gate side driver circuit or a gate driver, and thewirings GL can also be referred to as selection signal lines, gatelines, or the like.

The driver circuit 403 has a function of supplying image signals to thepixels pix. Specifically, the driver circuit 403 has a function ofsupplying image signals to the wirings SL, and the wirings SL have afunction of transmitting the image signals output from the drivercircuit 403 to the pixels pix. Note that the driver circuit 403 can bereferred to as a source side driver circuit or a source driver, and thewirings SL can also be referred to as image signal lines, source lines,or the like.

FIG. 20(B) illustrates a structure example of the pixel pix including alight-emitting element as a display element. The pixel pix illustratedin FIG. 20(B) includes transistors Tr31 and Tr32, a capacitor C31, and alight-emitting element LE. Note that although the transistors Tr31 andTr32 are of n-channel type here, the polarities of the transistors canbe changed as appropriate.

A gate of the transistor Tr31 is connected to the wiring GL, one of asource and a drain is connected to a gate of the transistor Tr32 and oneelectrode of the capacitor C31, and the other of the source and thedrain is connected to the wiring SL. One of a source and a drain of thetransistor Tr32 is connected to the other electrode of the capacitor C31and one electrode of the light-emitting element LE, and the other of thesource and the drain is connected to a wiring to which a potential Va issupplied. The other electrode of the light-emitting element LE isconnected to a wiring to which a potential Vc is supplied. Anode that isconnected to the one of the source and the drain of the transistor Tr31,the gate of the transistor Tr32, and the one electrode of the capacitorC31 is referred to as a node N31. A node that is connected to the one ofthe source and the drain of the transistor Tr32 and the other electrodeof the capacitor C31 is referred to as a node N32.

Here, the case where the potential Va is a high power supply potentialand the potential Vc is a low power supply potential is described. Thepotential Va and the potential Vc can each be a common potential to theplurality of pixels pix. Furthermore, the capacitor C31 functions as astorage capacitor for holding the potential of the node N31.

The transistor Tr31 has a function of controlling the supply of thepotential of the wiring SL to the node N31. Specifically, the potentialof the wiring GL is controlled to turn on the transistor Tr31, wherebythe potential of the wiring SL that corresponds to an image signal issupplied to the node N31 and written to the pixel pix. After that, thepotential of the wiring GL is controlled to turn off the transistorTr31, whereby the potential of the node N31 is held.

Then, the amount of current flowing between the source and the drain ofthe transistor Tr32 is controlled in accordance with the voltage betweenthe nodes N31 and N32, and the light-emitting element LE emits lightwith a luminance corresponding to the amount of flowing current.Accordingly, the gray level of the pixel pix can be controlled. Notethat the transistor Tr32 preferably operates in a saturation region.

As illustrated in FIG. 20(B), the pixel pix preferably includes twotransistors (Tr31 and Tr32). This structure can increase an apertureratio of a pixel in the case of a bottom emission structure to bedescribed later. Note that one embodiment of the present invention isnot limited thereto, and three or more transistors may be provided inthe pixel pix.

FIG. 20(C) illustrates a structure example of the pixel pix including aliquid crystal element as the display element. The pixel pix illustratedin FIG. 20(C) includes a transistor Tr33, a capacitor C32, and a liquidcrystal element LC. Note that although the transistor Tr33 is ofre-channel type here, the polarity of the transistor can be changed asappropriate.

A gate of the transistor Tr33 is connected to the wiring GL, one of asource and a drain is connected to one electrode of the liquid crystalelement LC and one electrode of the capacitor C32, and the other of thesource and the drain is connected to the wiring SL. The other electrodeof the liquid crystal element LC is connected to a wiring to which apotential Vcom is supplied. The other electrode of the capacitor C32 isconnected to a wiring to which a predetermined potential is supplied. Anode that is connected to the one of the source and the drain of thetransistor Tr33, the one electrode of the liquid crystal element LC, andthe one electrode of the capacitor C32 is referred to as a node N33.

The potential Vcom can be a common potential to the plurality of pixelspix. The potential Vcom may be the same as a potential of a wiringconnected to the other electrode of the capacitor C32. The capacitor C32functions as a storage capacitor for holding the potential of the nodeN33.

The transistor Tr33 has a function of controlling the supply of thepotential of the wiring SL to the node N33. Specifically, the potentialof the wiring GL is controlled to turn on the transistor Tr33, wherebythe potential of the wiring SL that corresponds to an image signal issupplied to the node N33 and written to the pixel pix. After that, thepotential of the wiring GL is controlled to turn off the transistorTr33, whereby the potential of the node N33 is held.

The liquid crystal element LC includes a pair of electrodes and a liquidcrystal layer containing a liquid crystal material to which a voltagebetween the pair of electrodes is applied. The alignment of liquidcrystal molecules included in the liquid crystal element LC changes inaccordance with the value of the voltage applied between the pair ofelectrodes, and thus the transmittance of the liquid crystal layer ischanged. Thus, the gray level of the pixel pix can be controlled bycontrolling a potential supplied from the wiring SL to the node N33.

The above-described operation is sequentially performed for every wiringGL, whereby an image for a first frame can be displayed.

Note that the selection of the wirings GL may be performed by aprogressive method or an interlace method. In addition, the supply ofimage signals to the wirings SL may be performed by dot sequentialdriving in which image signals are sequentially supplied to the wiringsSL, or may be performed by line sequential driving in which imagesignals are concurrently supplied to all the wirings SL. Alternatively,the supply of image signals may be sequentially performed for everyplural wirings SL.

After that, in a second frame period, an image is displayed by operationsimilar to that in a first frame period. Thus, the image displayed onthe pixel unit 401 is rewritten.

As a semiconductor used for the transistors included in the pixels pix,a Group 14 element such as silicon or germanium, a compoundsemiconductor such as gallium arsenide, an organic semiconductor, ametal oxide, or the like can be used. The semiconductor may be anon-single-crystal semiconductor (e.g., an amorphous semiconductor, amicrocrystalline semiconductor, or a polycrystalline semiconductor) or asingle crystal semiconductor.

Here, the transistors included in the pixels pix preferably contain anamorphous semiconductor, in particular, hydrogenated amorphous silicon(a-Si:H) in channel formation regions. Transistors using an amorphoussemiconductor easily deal with the increase in substrate area; thus,when a large-screen display device that is compatible with 4K2Kbroadcasting or 8K4K broadcasting, for example, is manufactured, themanufacturing process can be simplified.

Furthermore, a transistor including a metal oxide in a channel formationregion (an OS transistor) can be used as each of the transistorsincluded in the pixels pix. An OS transistor has higher field-effectmobility than a transistor including hydrogenated amorphous silicon. Inaddition, an OS transistor does not require a crystallization processthat has been necessary for a transistor using polycrystalline siliconor the like.

Since an OS transistor has an extremely low off-state current, in thecase where an OS transistor is used as the transistor Tr31, an imagesignal can be held in the pixel pix for an extremely long period. Thisenables the update frequency of an image signal to be extremely low in aperiod when there is no change in the image displayed on the pixel unit401 or a period when the change is at a certain level or lower. Theupdate frequency of an image signal can be set less than or equal toonce every 0.1 seconds, less than or equal to once every second, or lessthan or equal to once every 10 seconds, for example. In particular, whena large number of pixels pix are provided to be compatible with 4K2Kbroadcasting or 8K4K broadcasting, or the like, reducing the powerconsumption by skipping update of an image signal is effective.

<Structure Example 2 of Display Device>

A display device including a plurality of display panels can be used forthe display unit 20. FIG. 21 illustrates a structure example of adisplay device 410 including a plurality of display panels DP.

The plurality of display panels DP included in the display device 410each have a function of displaying an image on the basis of an imagesignal input from the signal generation unit 30 (see FIG. 1). FIG. 21illustrates the display device 410 including the display panels DParranged in I rows and J columns (I and J are natural numbers). Notethat the display panels DP can control display independent of eachother.

An image display region can be enlarged by displaying one image usingthe plurality of display panels DP. For example, the display unit 20with a screen diagonal of 30 inches or more, 40 inches or more, 50inches or more, or 60 inches or more can be obtained. A high-resolutiondisplay unit with full high definition or higher, for example, 4K2K,8K4K, or higher can also be obtained.

In the case where an image is displayed using the plurality of displaypanels DP, each of the display panels DP is not necessarily large. Thus,an apparatus for manufacturing the display panels does not need to beincreased in size. In addition, since an apparatus for manufacturingsmall- and medium-size display panels can be used, there is no need toprepare equipment for large-size display devices, which reducesmanufacturing costs. In addition, a decrease in yield caused by anincrease in the size of a display panel can be prevented.

The signal SD that is generated in the signal generation unit 30 isdivided into I x J signals SDdiv, and the signals SDdiv are supplied tothe display panels DP. Each of the display panels DP displays apredetermined image on the basis of the signal SDdiv. Thus, one image isdisplayed using the plurality of display panels DP.

Each of the display panels DP includes the pixel unit 401, the drivercircuit 402, and the driver circuit 403 illustrated in FIG. 20(A).

In the case where the plurality of display panels DP are provided in thedisplay device 410, the plurality of display panels DP are preferablyarranged such that the display region is continuous over adjacentdisplay panels DP. FIG. 22 illustrates a structure example and anarrangement example of the display panels DP.

The display panel DP illustrated in FIG. 22(A) includes a display region421, and a region 422 transmitting visible light and a region 423blocking visible light that are adjacent to the display region 421. FIG.22(A) illustrates an example where the display panel DP is provided withan FPC (Flexible Printed Circuit) 424.

The display region 421 includes the plurality of pixels pix (notillustrated). In the region 422, for example, a pair of substratesincluded in the display panel DP, a sealant for sealing the displayelement interposed between the pair of substrates, and the like may beprovided. Here, for a member provided in the region 422, a material witha visible-light-transmitting property is used. In the region 423, forexample, a wiring connected to the pixels pix included in the displayregion 421 or the like can be provided. In addition, the driver circuit402 or the driver circuit 403 may be provided in the region 423.Furthermore, a terminal connected to the FPC 424, a wiring connected tothe terminal, or the like may be provided in the region 423.

FIG. 22(B) illustrates the arrangement example of the display panels DPillustrated in FIG. 22(A). For example, four adjacent display panelsDPa, DPb, DPc, and DPd are illustrated here. FIG. 22(C) is a schematicperspective view of the four display panels seen from the side oppositeto the display surface side.

Each of the display panels DP is provided to have a region overlappingwith the other display panels DP. Specifically, the display panels DPa,DPb, DPc, and DPd are arranged such that the region 422 transmittingvisible light that is included in one display panel DP has a regionoverlapping with and located over the display region 421 (on the displaysurface side) of another display panel DP. The display panels DPa, DPb,DPc, and DPd are arranged also such that the region 423 blocking visiblelight that is included in one display panel DP is prevented fromoverlapping with and being located over the display region 421 ofanother display panel DP.

More specifically, a region along a short side of a display region 421 aof the display panel DPa is provided to overlap with part of a region422 b of the display panel DPb. In addition, a region along a long sideof the display region 421 a of the display panel DPa is provided tooverlap with part of a region 422 c of the display panel DPc. Moreover,a region 422 d of the display panel DPd is provided to overlap with aregion along a long side of a display region 421 b of the display panelDPb and a region along a short side of a display region 421 c of thedisplay panel DPc.

The region 422 transmitting visible light overlaps with and is locatedover the display region 421 in such a manner; thus, the whole displayregion 421 can be viewed from the display surface side. Thus, a regionwhere the display regions 421 a, 421 b, 421 c, and 421 d are arrangedcontinuously without seams can be used as a display region 425 of thedisplay device 410.

Note that it is preferable that the pair of substrates used for thedisplay panels DP have flexibility and the display panels DP haveflexibility. Thus, as illustrated in FIGS. 22(B) and 22(C), for example,part of the display panel DPa on the FPC 424 a side is curved, wherebythe FPC 424 a can underlap the display region 421 b of the adjacentdisplay panel DPb. As a result, the FPC 424 a can be placed withoutphysical interference with the rear surface of the display panel DPb.Furthermore, when the display panel DPa and the display panel DPboverlap with and are bonded to each other, it is not necessary toconsider the thickness of the FPC 424 a; thus, a difference in theheight between the top surface of the region 422 b of the display panelDPb and the top surface of the display region 421 a of the display panelDPa can be reduced. As a result, the end portion of the display panelDPb over the display region 421 a is prevented from being viewed.

Moreover, each display panel DP is made flexible, in which case thedisplay panel DPb can be curved gently so that the top surface of thedisplay region 421 b of the display panel DPb is level with the topsurface of the display region 421 a of the display panel DPa. Thus, thedisplay regions can be level with each other except in the vicinity of aregion where the display panel DPa and the display panel DPb overlapwith each other, and the display quality of an image displayed on thedisplay region 425 can be improved.

Note that to reduce the step between two adjacent display panels DP, thethicknesses of the display panels DP are preferably small. For example,the thicknesses of the display panels DP are preferably less than orequal to 1 mm, further preferably less than or equal to 300 μm, stillfurther preferably less than or equal to 100 μm.

Furthermore, when the display panels DP are made flexible, a displayregion that includes the plurality of display panels DP and has a curvedsurface can be formed. For example, as illustrated in FIG. 23, theflexible display panels DP are provided along a curved surface of acylindrical pillar 430, whereby the display region having a curvedsurface can be formed.

This embodiment can be combined with the description of the otherembodiments as appropriate.

Embodiment 6

In this embodiment, a specific structure example of the display devicedescribed in the above embodiment is described.

FIG. 24 illustrates a structure example of a display device 300. Thedisplay device 300 has a function of displaying an image with the use ofa light-emitting element.

The display device 300 includes an electrode 308, and the electrode 308is connected to a terminal included in an FPC 309 via an anisotropicconductive layer 310. The electrode 308 is also connected to a wiring304 through an opening formed in an insulating layer 307, an insulatinglayer 306, and an insulating layer 305. The electrode 308 is formedusing the same material as that of an electrode layer 341.

The pixel pix provided over a substrate 301 includes the transistor Tr32(see FIG. 20(B)). The transistor Tr32 is provided over an insulatinglayer 302. The transistor Tr32 includes an electrode 331 provided overthe insulating layer 302, and an insulating layer 303 is formed over theelectrode 331. A semiconductor layer 332 is provided over the insulatinglayer 303. An electrode 333 and an electrode 334 are provided over thesemiconductor layer 332, the insulating layer 305 and the insulatinglayer 306 are provided over the electrode 333 and the electrode 334, andan electrode 335 is provided over the insulating layer 305 and theinsulating layer 306. The electrode 333 and the electrode 334 are formedusing the same material as that of the wiring 304.

In the transistor Tr32, the electrode 331 functions as a gate electrode,the electrode 333 functions as one of a source electrode and a drainelectrode, the electrode 334 functions as the other of the sourceelectrode and the drain electrode, and the electrode 335 functions as aback gate electrode.

The transistor Tr32 has a bottom gate structure and includes a backgate, which can increase the on-state current. Moreover, the thresholdvoltage of the transistor can be controlled. The electrode 335 may beomitted in some cases to simplify the manufacturing process.

As a semiconductor material used for the transistor, for example, aGroup 14 element (silicon, germanium, or the like) or a metal oxide canbe used. A semiconductor containing silicon, a semiconductor containinggallium arsenide, a metal oxide containing indium, or the like can betypically used.

Silicon can be used as a semiconductor in which a channel of thetransistor is formed, for example. It is particularly preferable to useamorphous silicon as silicon. By using amorphous silicon, transistorscan be formed over a large substrate in high yield, resulting inexcellent mass productivity.

Alternatively, silicon having crystallinity, such as microcrystallinesilicon, polycrystalline silicon, or single crystal silicon, can beused. In particular, polycrystalline silicon can be formed at a lowertemperature than single crystal silicon and has higher field-effectmobility and higher reliability than amorphous silicon.

As a semiconductor in which a channel of the transistor is formed, inparticular, a metal oxide having a wider band gap than silicon can alsobe used. A semiconductor material having a wider band gap and a lowercarrier density than silicon is preferably used because the off-statecurrent of the transistor can be reduced.

Owing to its low off-state current, a transistor using a metal oxidehaving a wider band gap than silicon enables long-term holding ofcharges stored in a capacitor that is series-connected to thetransistor. The use of such a transistor in pixels allows a drivercircuit to stop while the gray level of an image displayed on eachdisplay region is maintained. As a result, the display device withsignificantly reduced power consumption can be obtained.

The metal oxide preferably includes, for example, a material representedby an In-M-Zn— based oxide that contains at least indium, zinc, and M (ametal such as aluminum, titanium, gallium, germanium, yttrium,zirconium, lanthanum, cerium, tin, neodymium, or hafnium). In order toreduce variations in electrical characteristics of the transistor usingthe metalloid oxide, a stabilizer is preferably contained in addition tothem.

Examples of the stabilizer include gallium, tin, hafnium, aluminum, andzirconium. Other examples of the stabilizer include lanthanoid such aslanthanum, cerium, praseodymium, neodymium, samarium, europium,gadolinium, terbium, dysprosium, holmium, erbium, thulium, ytterbium, orlutetium.

As a metal oxide contained in the semiconductor layer, for example, anIn—Ga—Zn-based oxide, an In—Al—Zn-based oxide, an In—Sn—Zn-based oxide,an In—Hf—Zn-based oxide, an In—La—Zn— based oxide, an In—Ce—Zn-basedoxide, an In—Pr—Zn-based oxide, an In—Nd—Zn-based oxide, anIn—Sm—Zn-based oxide, an In—Eu—Zn-based oxide, an In—Gd—Zn-based oxide,an In—Tb—Zn-based oxide, an In—Dy—Zn-based oxide, an In—Ho—Zn-basedoxide, an In—Er—Zn-based oxide, an In—Tm—Zn-based oxide, anIn—Yb—Zn-based oxide, an In—Lu—Zn-based oxide, an In—Sn—Ga—Zn-basedoxide, an In—Hf—Ga—Zn-based oxide, an In—Al—Ga—Zn-based oxide, anIn—Sn—Al—Zn-based oxide, an In—Sn—Hf—Zn-based oxide, or anIn—Hf—Al—Zn-based oxide can be used.

Note that here, an In—Ga—Zn-based oxide means an oxide containing In,Ga, and Zn as its main components and there is no limitation on theratio of In to Ga and Zn. Furthermore, a metal element in addition toIn, Ga, and Zn may be contained.

The semiconductor layer and the conductive layer may include the samemetal elements contained in the above oxides. The use of the same metalelements for the semiconductor layer and the conductive layer can reducethe manufacturing costs. For example, the use of metal oxide targetswith the same metal composition can reduce the manufacturing costs. Inaddition, the same etching gas or the same etchant can be used inprocessing the semiconductor layer and the conductive layer. Note thateven when the semiconductor layer and the conductive layer include thesame metal elements, they have different compositions in some cases. Forexample, a metal element in a film may be released during themanufacturing process of the transistor and the capacitor, resulting indifferent metal compositions.

The energy gap of the metal oxide contained in the semiconductor layeris preferably greater than or equal to 2 eV, further preferably greaterthan or equal to 2.5 eV, still further preferably greater than or equalto 3 eV. With the use of a metal oxide having such a wide energy gap,the off-state current of the transistor can be reduced.

In the case where the metal oxide contained in the semiconductor layeris an In-M-Zn oxide, the atomic ratio of the metal elements of asputtering target used for forming a film of the In-M-Zn oxidepreferably satisfies In M and Zn M. As the atomic ratio of the metalelements of such a sputtering target, In:M:Zn=1:1:1, In:M:Zn=1:1:1.2,In:M:Zn=3:1:2, 4:2:4.1, and the like are preferable. Note that theatomic ratio in the formed semiconductor layer varies from the aboveatomic ratio of the metal elements contained in the sputtering targetwithin a range of ±40% as an error.

A metal oxide with a low carrier density is preferably used for thesemiconductor layer. For example, it is possible to use, for thesemiconductor layer, a metal oxide whose carrier density is lower thanor equal to 1×10¹⁷/cm³, preferably lower than or equal to 1×10¹⁵/cm³,further preferably lower than or equal to 1×10¹³/cm³, still furtherpreferably lower than or equal to 1×10¹¹/cm³, even further preferablylower than 1×10¹⁰/cm³, and higher than or equal to 1×10⁻⁹/cm³. Such asemiconductor layer has a low impurity concentration and a low densityof defect states and thus has stable characteristics.

Note that without limitation to the above, a material with anappropriate composition can be used in accordance with requiredsemiconductor characteristics and electrical characteristics (e.g.,field-effect mobility and threshold voltage) of a transistor. To obtainthe required semiconductor characteristics of the transistor, it ispreferred that the carrier density, the impurity concentration, thedefect density, the atomic ratio of a metal element to oxygen, theinteratomic distance, the density, and the like of the semiconductorlayer be set to appropriate values.

When silicon or carbon that is one of Group 14 elements is contained inthe metal oxide contained in the semiconductor layer, oxygen vacanciesare increased in the semiconductor layer, and the semiconductor layerbecomes n-type in some cases. Thus, the concentration of silicon orcarbon (the concentration measured by secondary ion mass spectrometry)in the semiconductor layer is preferably lower than or equal to 2×10¹⁸atoms/cm³, further preferably lower than or equal to 2×10¹⁷ atoms/cm³.

Moreover, an alkali metal and an alkaline earth metal might generatecarriers when bonded to a metal oxide, in which case the off-statecurrent of the transistor might be increased. Therefore, theconcentration of an alkali metal or an alkaline earth metal of thesemiconductor layer, which is measured by secondary ion massspectrometry, is preferably lower than or equal to 1×10¹⁸ atoms/cm³,further preferably lower than or equal to 2×10¹⁶ atoms/cm³.

The metal oxide may have a non-single-crystal structure, for example.Examples of non-single-crystal structures include a polycrystallinestructure, a microcrystalline structure, and an amorphous structure.Among the non-single-crystal structures, the amorphous structure has thehighest density of defect states.

A metal oxide having an amorphous structure has disordered atomicarrangement and no crystalline component, for example. Alternatively, anoxide film having an amorphous structure has, for example, a completelyamorphous structure and no crystal part.

Note that the metal oxide may be a mixed film including two or more of aregion having an amorphous structure, a region having a microcrystallinestructure, a region having a polycrystalline structure, and a regionhaving a single crystal structure. The mixed film has, for example, asingle-layer structure or a stacked-layer structure including two ormore of the above regions in some cases.

The semiconductor materials described above can be used not only in thetransistor Tr32 but also in the transistor Tr31 in FIG. 20(B) and thetransistor Tr33 in FIG. 20(C).

The display device 300 includes the capacitor C31. The capacitor C31includes a region where the electrode 334 and an electrode 336 overlapwith each other with the insulating layer 303 positioned therebetween.The electrode 336 is formed using the same material as that of theelectrode 331.

FIG. 24 illustrates an example of a display device including, as adisplay element, a light-emitting element such as an EL element. ELelements are classified into organic EL elements and inorganic ELelements.

In an organic EL element, by voltage application, electrons from oneelectrode and holes from the other electrode are injected to the ELlayer. The carriers (electrons and holes) are recombined, and thus, alight-emitting organic compound forms an excited state, and light isemitted when the excited state returns to a ground state. Owing to sucha mechanism, this light-emitting element is referred to as acurrent-excitation light-emitting element. Note that other than thelight-emitting compound, the EL layer may further contain a substancewith a high hole-injection property, a substance with a highhole-transport property, a hole-blocking material, a substance with ahigh electron-transport property, a substance with a highelectron-injection property, a substance with a bipolar property (asubstance with a high electron- and hole-transport property), or thelike. The EL layer can be formed by an evaporation method (including avacuum evaporation method), a transfer method, a printing method, aninkjet method, a coating method, and the like.

The inorganic EL elements are classified according to their elementstructures into a dispersion-type inorganic EL element and a thin-filminorganic EL element. A dispersion-type inorganic EL element includes alight-emitting layer where particles of a light-emitting material aredispersed in a binder, and its light emission mechanism isdonor-acceptor recombination type light emission that utilizes a donorlevel and an acceptor level. A thin-film inorganic EL element has astructure in which a light-emitting layer is sandwiched betweendielectric layers, which are further sandwiched between electrodes, andits light emission mechanism is localization type light emission thatutilizes inner-shell electron transition of metal ions.

FIG. 24 illustrates an example where an organic EL element is used asthe light-emitting element LE.

In FIG. 24, the light-emitting element LE is connected to the transistorTr32 provided in the pixel pix. Although the light-emitting element LEhas a stacked-layer structure including the electrode layer 341, alight-emitting layer 342, and an electrode layer 343, one embodiment ofthe present invention is not limited to this structure. The structure ofthe light-emitting element LE can be changed as appropriate depending onthe direction in which light is extracted from the light-emittingelement LE, or the like.

A partition wall 344 is formed using an organic insulating material oran inorganic insulating material. It is particularly preferable that aphotosensitive resin material be used and an opening be formed over theelectrode layer 341 so that a side surface of the opening becomes aninclined surface with continuous curvature.

The light-emitting layer 342 may be composed of a single layer or astack of a plurality of layers.

A protective layer may be formed over the electrode layer 343 and thepartition wall 344 in order to prevent entry of oxygen, hydrogen,moisture, carbon dioxide, or the like into the light-emitting elementLE. The protective layer can be formed using silicon nitride, siliconnitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride,aluminum nitride oxide, DLC (Diamond Like Carbon), or the like. Inaddition, in a space that is enclosed by the substrate 301, a substrate312, and a sealant 311, a filler 345 is provided and sealed. It ispreferable that the light-emitting element be packaged (sealed) with aprotective film (e.g., a laminate film or an ultraviolet curable resinfilm) or a cover member in this manner with high air-tightness andlittle degasification so that the light-emitting element is not exposedto the outside air.

As the filler 345, an ultraviolet curable resin or a thermosetting resinas well as an inert gas such as nitrogen or argon can be used; forexample, PVC (polyvinyl chloride), an acrylic resin, polyimide, an epoxyresin, a silicone resin, PVB (polyvinyl butyral), or EVA (ethylene vinylacetate) can be used. A drying agent may be contained in the filler 345.

A glass material such as a glass frit or a resin material such as acurable resin that is curable at room temperature, such as atwo-component-mixture-type resin, a light curable resin, and athermosetting resin can be used for the sealant 311. A drying agent maybe contained in the sealant 311.

In addition, if needed, an optical film such as a polarizing plate, acircularly polarizing plate (including an elliptically polarizingplate), a retardation plate (a quarter-wave plate or a half-wave plate),or a color filter may be provided as appropriate on a light-emittingsurface of the light-emitting element. Furthermore, the polarizing plateor the circularly polarizing plate may be provided with ananti-reflection film. For example, anti-glare treatment by whichreflected light can be diffused by projections and depressions on asurface to reduce the glare can be performed.

When the light-emitting element has a microcavity structure, light withhigh color purity can be extracted. Furthermore, when a microcavitystructure and a color filter are used in combination, the glare can bereduced and visibility of a display image can be increased.

For the electrode layer 341 and the electrode layer 343, it is possibleto use a conductive material with a light-transmitting property, such asindium oxide containing tungsten oxide, indium zinc oxide containingtungsten oxide, indium oxide containing titanium oxide, indium tinoxide, indium tin oxide containing titanium oxide, indium zinc oxide, orindium tin oxide to which silicon oxide is added.

The electrode layer 341 and the electrode layer 343 can be formed usingone or more kinds selected from metals such as tungsten (W), molybdenum(Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum(Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum(Pt), aluminum (Al), copper (Cu), and silver (Ag); alloys thereof; ormetal nitrides thereof.

The electrode layer 341 and the electrode layer 343 can be formed usinga conductive composition containing a conductive macromolecule (alsoreferred to as a conductive polymer). As the conductive macromolecule,what is called a t-electron conjugated conductive macromolecule can beused. Examples include polyaniline or a derivative thereof, polypyrroleor a derivative thereof, polythiophene or a derivative thereof, and acopolymer of two or more of aniline, pyrrole, and thiophene or aderivative thereof.

In order to extract light emitted from the light-emitting element LE tothe outside, at least one of the electrode layer 341 and the electrodelayer 343 is transparent. In accordance with how to extract light, thestructures of display devices are classified into a top emissionstructure, a bottom emission structure, and a dual emission structure.In the top emission structure, light is extracted from the substrate 312side. In the bottom emission structure, light is extracted from thesubstrate 301 side. In the dual emission structure, light is extractedfrom both the substrate 312 side and the substrate 301 side. In the caseof the top emission structure, for example, the electrode layer 343 istransparent. In the case of the bottom emission structure, for example,the electrode layer 341 is transparent. In the case of the dual emissionstructure, for example, the electrode layer 341 and the electrode layer343 are transparent.

FIG. 25 illustrates a cross-sectional view in which a top-gatetransistor is provided as the transistor Tr32 illustrated in FIG. 24. Inthe transistor Tr32 in FIG. 25, the electrode 331 functions as a gateelectrode, the electrode 333 functions as one of a source electrode anda drain electrode, and the electrode 334 functions as the other of thesource electrode and the drain electrode.

For the details of the other components in FIG. 25, refer to thedescription of FIG. 24.

In the case where a light-emitting element is used as the displayelement as illustrated in FIG. 24 and FIG. 25, the display device 300can be referred to as a light-emitting device. Although the case where alight-emitting element is used as the display element is described inthis embodiment, a liquid crystal element can be used as the displayelement as illustrated in FIG. 20(C).

This embodiment can be combined with the description of the otherembodiments as appropriate.

Embodiment 7

In this embodiment, a specific structure example of the display devicedescribed in the above embodiment is described.

The display device of this embodiment has a function of displaying animage with the use of a light-emitting element. In this embodiment, inparticular, an example where a micro LED is used as the light-emittingelement is described. Note that in this embodiment, a micro LED having adouble heterojunction is described. Note that one embodiment of thepresent invention is not limited thereto, and a micro LED having aquantum well junction may be used.

When a micro LED is used as the display element, the power consumptionof a display device can be reduced. Furthermore, the display device canbe thinner and more lightweight. Moreover, the display device using themicro LED as the display element has high contrast and a wide viewingangle; thus, the display quality can be improved.

The area of a light-emitting region of a micro LED is preferably lessthan or equal to 1 mm², further preferably less than or equal to 10000μm², still further preferably less than or equal to 3000 μm², evenfurther preferably less than or equal to 700 μm².

FIG. 26(A1) illustrates a cross-sectional view of a display device 350A.FIG. 26(A2) illustrates an enlarged view of a light-emitting element LE1and the vicinity thereof in the display device 350A.

FIG. 26(B1) illustrates a cross-sectional view of a display device 350B.FIG. 26(B2) illustrates an enlarged view of a light-emitting element LE2and the vicinity thereof in the display device 350B.

FIG. 27(A1) illustrates a cross-sectional view of a display device 350C.FIG. 27(A2) illustrates an enlarged view of a light-emitting element LE3and the vicinity thereof in the display device 350C.

FIG. 27(B) illustrates a cross-sectional view of a display device 350D.A light-emitting element LE4 included in the display device 350D has astructure similar to that of the light-emitting element LE2; thus, anenlarged view and the detailed description thereof are omitted.

Note that the description of Embodiment 6 can be referred to for thecomponents of the display device of this embodiment, which are similarto those in FIG. 24 or FIG. 25; therefore, the detailed description isomitted in some cases. For example, the structure of the display deviceof this embodiment except the pixel pix is similar to that in FIG. 24 orFIG. 25; therefore, the description of Embodiment 6 can be referred to.

The transistor Tr32 and the capacitor C31 included in the pixel pix inthe display device of this embodiment are similar to those in FIG. 24 orFIG. 25; therefore, the description of Embodiment 6 can be referred to.In particular, in the display device of this embodiment, a channelformation region of the transistor Tr32 preferably includes a metaloxide. As described above, a transistor including a metal oxide can havelow power consumption. Thus, a combination with a micro LED can achievea display device with significantly reduced power consumption.

Hereinafter, the structures of the light-emitting elements and theirvicinities in the drawings are described in detail.

The light-emitting element LE1 illustrated in FIG. 26(A1) and FIG.26(A2) includes an electrode 361, a clad layer 372, an active layer 373,a clad layer 374, and an electrode 363.

The electrode 361 is electrically connected to an electrode 351 througha bonding layer 371. The electrode 351 is electrically connected to theelectrode 334 included in the transistor Tr32. That is, the electrode361 functions as a pixel electrode. The bonding layer 371 is preferablyformed using a material having high conductivity.

The electrode 363 is electrically connected to an electrode 353 throughthe bonding layer 371. The electrode 351 and the electrode 353 areelectrically insulated from each other by the partition walls 344. Theelectrode 363 functions as a common electrode.

The active layer 373 is sandwiched between the clad layer 372 and theclad layer 374. In the active layer 373, electrons and holes are bondedto emit light. That is, the active layer 373 can be referred to as alight-emitting layer. One of the clad layer 372 and the clad layer 374is an n-type clad layer, and the other is a p-type clad layer. Thestacked-layer structure including the clad layer 372, the active layer373, and the clad layer 374 is formed to emit light of red, yellow,green, blue, or the like. For example, for the stacked-layer structure,a compound of gallium and phosphorus, a compound of gallium and arsenic,a compound of gallium, aluminum, and arsenic, a compound of aluminum,gallium, indium, and phosphorus, gallium nitride, a compound of indiumand gallium nitride, a compound of selenium and zinc, or the like can beused. When the above-described stacked-layer structure including theclad layer 372, the active layer 373, and the clad layer 374 is formedto emit light of red, yellow, green, blue, or the like, a step offorming a coloring film such as a color filter is not necessary.Consequently, the manufacturing costs of display devices can be reduced.

The light-emitting element LE1 may be fixed to the partition wall 344with a sealant 346. This can prevent display defects or the like of thelight-emitting element LE1.

The light-emitting element LE1 illustrated in FIG. 26(A1) and FIG.26(A2) has a bottom emission structure and emits light to the substrate301 side. Thus, the electrode 351, the bonding layer 371, the electrode353, the electrode 361, and the electrode 363 are each formed using aconductive material that transmits visible light.

For example, the light-emitting element LE1 is formed over a carriersubstrate and transferred from the carrier substrate to the substrate301 (specifically, over the electrode 351, the electrode 353, and thepartition wall 344). The light-emitting elements LE1 may be formed overdifferent carrier substrates for the respective colors and transferredto the substrate 301. Alternatively, a plurality of light-emittingelements LE1 that emit light of respective different colors may beformed over one carrier substrate, and then the plurality oflight-emitting elements LE1 may be collectively transferred to thesubstrate 301.

The light-emitting element LE2 illustrated in FIG. 26(B1) and FIG.26(B2) includes the electrode 361, the clad layer 372, the active layer373, the clad layer 374, and an electrode 362. As illustrated in FIG.26(B1), a plurality of light-emitting elements may be electricallyconnected to one transistor Tr32.

The electrode 361 is electrically connected to the electrode 351 throughthe bonding layer 371. The electrode 351 is electrically connected tothe electrode 334 included in the transistor Tr32. That is, theelectrode 361 functions as a pixel electrode.

The electrode 362 is electrically connected to an electrode 357 throughthe electrode 353. The electrode 351 and the electrode 357 areelectrically insulated from each other by an insulating layer 355. Theelectrode 351 and the electrode 353 are electrically insulated from eachother by an insulating layer 356. The electrode 362 functions as acommon electrode.

The active layer 373 is sandwiched between the clad layer 372 and theclad layer 374.

The light-emitting element LE2 illustrated in FIG. 26(B1) and FIG.26(B2) has a top emission structure and emits light to the substrate 312side. Thus, the electrode 362 and the electrode 353 are each formedusing a conductive material that transmits visible light. Since theelectrode 351, the electrode 357, and the electrode 361 do notnecessarily have light-transmitting properties, the electrodes can beformed using a metal material that blocks visible light. Furthermore,the transistor Tr32 or the capacitor C31 can be provided to overlap withthe light-emitting element LE2; thus, an aperture ratio can beincreased.

For example, the light-emitting element LE2 is formed over the carriersubstrate and transferred from the carrier substrate to the substrate301 (specifically, over the electrode 351, the electrode 357, and theinsulating layer 355). After the transfer, forming the electrode 353over the light-emitting element LE2 makes it possible to electricallyconnect the electrode 362 to the electrode 357.

The light-emitting element LE3 illustrated in FIG. 27(A1) and FIG.27(A2) includes the electrode 361, the clad layer 372, the active layer373, the clad layer 374, and the electrode 363.

The electrode 361 is electrically connected to the electrode 351 throughthe bonding layer 371. The electrode 351 is electrically connected tothe electrode 334 included in the transistor Tr32. That is, theelectrode 361 functions as a pixel electrode.

The electrode 363 is electrically connected to the electrode 353 throughthe bonding layer 371. The electrode 351 and the electrode 353 areelectrically insulated from each other by the partition walls 344. Theelectrode 363 functions as a common electrode.

The active layer 373 is sandwiched between the clad layer 372 and theclad layer 374.

In the light-emitting element LE3, the electrode 361 and the electrode363 are formed using different materials. The clad layer 372 and theactive layer 373 overlap with the electrode 361 and do not overlap withthe electrode 363.

The light-emitting element LE3 has a bottom emission structure and emitslight to the substrate 301 side. Thus, the electrode 351, the bondinglayer 371, and the electrode 361 are each formed using a conductivematerial that transmits visible light. Since the electrode 363 does notoverlap with a light-emitting region of the light-emitting element LE3,the electrode 363 does not necessarily have a light-transmittingproperty.

The light-emitting element LE4 illustrated in FIG. 27(B) has a structuresimilar to that of the light-emitting element LE2. As illustrated inFIG. 27(B), one light-emitting element may be electrically connected toone transistor Tr32.

As described above, the display device of this embodiment uses a microLED as the display element. Thus, a display device with low powerconsumption and high display quality can be provided. In addition, acombination with the semiconductor device of one embodiment of thepresent invention enables a stereoscopic image to be displayed with highquality and low power consumption.

This embodiment can be combined with the description of the otherembodiments as appropriate.

Embodiment 8

In this embodiment, a metal oxide that can be used for the OS transistordescribed in the above embodiment is described. In particular, thedetails of a metal oxide and a CAC (Cloud-Aligned Composite)-OS aredescribed below.

A CAC-OS or a CAC-metal oxide has a conducting function in a part of thematerial and an insulating function in a part of the material, and has afunction of a semiconductor as the whole material. Note that in the casewhere the CAC-OS or the CAC-metal oxide is used in a channel formationregion of a transistor, the conducting function is to allow electrons(or holes) serving as carriers to flow, and the insulating function isto not allow electrons serving as carriers to flow.

By the complementary action of the conducting function and theinsulating function, a switching function (On/Off function) can be givento the CAC-OS or the CAC-metal oxide. In the CAC- or the CAC-metaloxide, separation of the functions can maximize each function.

In addition, the CAC-OS or the CAC-metal oxide includes conductiveregions and insulating regions. The conductive regions have theabove-described conducting function, and the insulating regions have theabove-described insulating function. In some cases, the conductiveregions and the insulating regions in the material are separated at thenanoparticle level. In some cases, the conductive regions and theinsulating regions are unevenly distributed in the material. Moreover,the conductive regions are sometimes observed to be coupled in acloud-like manner with their boundaries blurred.

Furthermore, in the CAC-OS or the CAC-metal oxide, the conductiveregions and the insulating regions each having a size greater than orequal to 0.5 nm and less than or equal to 10 nm, preferably greater thanor equal to 0.5 nm and less than or equal to 3 nm are dispersed in thematerial in some cases.

The CAC-OS or the CAC-metal oxide is composed of components havingdifferent band gaps. For example, the CAC-OS or the CAC-metal oxide iscomposed of a component having a wide gap due to the insulating regionand a component having a narrow gap due to the conductive region. Whencarriers flow in this composition, the carriers mainly flow in thecomponent having a narrow gap. Moreover, the component having a narrowgap complements the component having a wide gap, and carriers also flowin the component having a wide gap in conjunction with the componenthaving a narrow gap. Therefore, in the case where the above-describedCAC-OS or CAC-metal oxide is used in a channel formation region of atransistor, the transistor in the on state can achieve high currentdriving capability, that is, high on-state current and high field-effectmobility.

In other words, the CAC-OS or the CAC-metal oxide can also be called amatrix composite or a metal matrix composite.

The CAC-OS refers to one composition of a material in which elementsconstituting a metal oxide are unevenly distributed with a size greaterthan or equal to 0.5 nm and less than or equal to 10 nm, preferablygreater than or equal to 1 nm and less than or equal to 2 nm, or asimilar size, for example. Note that a state in which one or more metalelements are unevenly distributed in a metal oxide and regions includingthe metal element(s) are mixed with a size greater than or equal to 0.5nm and less than or equal to 10 nm, preferably greater than or equal to1 nm and less than or equal to 2 nm, or a similar size is hereinafterreferred to as a mosaic pattern or a patch-like pattern.

Note that a metal oxide preferably contains at least indium. Inparticular, indium and zinc are preferably contained. Moreover, inaddition to them, one kind or a plurality of kinds selected fromaluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon,titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum,cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the likemay be contained.

For example, a CAC-OS in an In—Ga—Zn oxide (an In—Ga—Zn oxide with theCAC-OS composition may be particularly referred to as CAC-IGZO) has acomposition in which materials are separated into indium oxide(hereinafter, InO_(X1) (X1 is a real number greater than 0)) or indiumzinc oxide (hereinafter, In_(X2)Zn_(Y2)O_(Z4) (X2, Y2, and Z2 are realnumbers greater than 0)) and gallium oxide (hereinafter, GaO_(X3) (X3 isa real number greater than 0)) or gallium zinc oxide (hereinafter,Ga_(X4)Zn_(Y4)O_(Z4) (X4, Y4, and Z4 are real numbers greater than 0))so that a mosaic pattern is formed, and mosaic-like InO_(X1) orIn_(X2)Zn_(Y2)O₂₂ is evenly distributed in the film (which ishereinafter also referred to as cloud-like).

That is, the CAC-OS is a composite metal oxide having a composition inwhich a region including GaO_(X3) as a main component and a regionincluding In_(X2)Zn_(Y2)O_(Z2) or InO_(X1) as a main component aremixed. Note that in this specification, for example, when the atomicratio of In to an element M in a first region is higher than the atomicratio of In to the element M in a second region, the first region isregarded as having a higher In concentration than the second region.

Note that IGZO is a commonly known name and sometimes refers to onecompound formed of In, Ga, Zn, and O. A typical example is a crystallinecompound represented by InGaO₃(ZnO)_(m1) (m1 is a natural number) orIn_((1+x0))Ga_((1-x0))O₃(ZnO)_(m0)(−1≤x0≤1; m0 is a given number).

The above crystalline compound has a single crystal structure, apolycrystalline structure, or a CAAC (c-axis aligned crystal) structure.Note that the CAAC structure is a crystal structure in which a pluralityof IGZO nanocrystals have c-axis alignment and are connected in the a-bplane direction without alignment.

On the other hand, the CAC-OS relates to the material composition of ametal oxide. The CAC-OS refers to a composition in which, in thematerial composition containing In, Ga, Zn, and O, some regions thatinclude Ga as a main component and are observed as nanoparticles andsome regions that include In as a main component and are observed asnanoparticles are randomly dispersed in a mosaic pattern. Therefore, thecrystal structure is a secondary element for the CAC-OS.

Note that the CAC-OS is regarded as not including a stacked-layerstructure of two or more kinds of films with different compositions. Forexample, a structure formed of two layers of a film including In as amain component and a film including Ga as a main component is notincluded.

Note that a clear boundary cannot sometimes be observed between theregion including GaO_(X3) as a main component and the region includingIn_(X2)Zn_(Y2)O_(Z2) or InO_(X1) as a main component.

Note that in the case where one kind or a plurality of kinds selectedfrom aluminum, yttrium, copper, vanadium, beryllium, boron, silicon,titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum,cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the likeare contained instead of gallium, the CAC-OS refers to a composition inwhich some regions that include the metal element(s) as a main componentand are observed as nanoparticles and some regions that include In as amain component and are observed as nanoparticles are randomly dispersedin a mosaic pattern.

The CAC-OS can be formed by a sputtering method under conditions where asubstrate is intentionally not heated, for example. Moreover, in thecase of forming the CAC-OS by a sputtering method, any one or moreselected from an inert gas (typically, argon), an oxygen gas, and anitrogen gas are used as a deposition gas. Furthermore, the ratio of theflow rate of an oxygen gas to the total flow rate of the deposition gasat the time of deposition is preferably as low as possible, and forexample, the flow rate ratio of the oxygen gas is preferably higher thanor equal to 0% and lower than 30%, further preferably higher than orequal to 0% and lower than or equal to 10%.

The CAC-OS is characterized in that no clear peak is observed inmeasurement using 0120 scan by an Out-of-plane method, which is one ofX-ray diffraction (XRD) measurement methods. That is, it is found fromthe X-ray diffraction that no alignment in the a-b plane direction andthe c-axis direction is observed in a measured region.

In addition, in an electron diffraction pattern of the CAC-OS which isobtained by irradiation with an electron beam with a probe diameter of 1nm (also referred to as a nanometer-sized electron beam), a ring-likehigh-luminance region and a plurality of bright spots in the ring regionare observed. It is therefore found from the electron diffractionpattern that the crystal structure of the CAC-OS includes an nc(nano-crystal) structure with no alignment in the plan-view directionand the cross-sectional direction.

Moreover, for example, it can be confirmed by EDX mapping obtained usingenergy dispersive X-ray spectroscopy (EDX) that an In—Ga—Zn oxide withthe CAC-OS composition has a composition in which regions includingGaO_(X3) as a main component and regions including In_(X2)Zn_(Y2)O_(Z2)or InO_(X1) as a main component are unevenly distributed and mixed.

The CAC-OS has a composition different from that of an IGZO compound inwhich the metal elements are evenly distributed, and has propertiesdifferent from those of the IGZO compound. That is, the CAC-OS has acomposition in which regions including GaO_(X3) or the like as a maincomponent and regions including In_(X2)Zn_(Y2)O_(Z2) or InO_(X1) as amain component are phase-separated from each other and form a mosaicpattern.

Here, a region including In_(X2)Zn_(Y2)O_(Z2) or InO_(X1) as a maincomponent has higher conductivity than a region including GaO_(X3) orthe like as a main component. In other words, when carriers flow throughregions including In_(X2)Zn_(Y2)O_(Z2) or InO_(X1) as a main component,the conductivity of an oxide semiconductor is exhibited. Accordingly,cloud-like distribution of regions including In_(X2)Zn_(Y2)O_(Z2) orInO_(X1) as a main component in an oxide semiconductor can achieve highfield-effect mobility (μ).

In contrast, a region including GaO_(X3) or the like as a main componenthas a higher insulating property than a region includingIn_(X2)Zn_(Y2)O_(Z2) or InO_(X1) as a main component. In other words,distribution of regions including GaO_(X3) or the like as a maincomponent in an oxide semiconductor can reduce leakage current andachieve favorable switching operation.

Accordingly, when the CAC-OS is used for a semiconductor element, theinsulating property derived from GaO_(X3) or the like and theconductivity derived from In_(X2)Zn_(Y2)O_(Z2) or InO_(X1) complementeach other, whereby high on-state current (I_(on)) and high field-effectmobility (μ) can be achieved.

Moreover, a semiconductor element using the CAC-OS has high reliability.Thus, the CAC-OS is most suitable for a variety of semiconductordevices.

This embodiment can be combined with the description of the otherembodiments as appropriate.

Embodiment 9

In this embodiment, electronic devices of embodiments of the presentinvention are described with reference to drawings.

The display unit 20 and the signal generation unit 30 described in theabove embodiment can be installed in the electronic devices illustratedas examples below. Thus, an electronic device that can display astereoscopic image can be provided.

Examples of the electronic devices include a digital camera, a digitalvideo camera, a digital photo frame, a mobile phone, a portable gameconsole, a portable information terminal, and an audio reproducingdevice, in addition to electronic devices with a relatively largescreen, such as a television device, a desktop or laptop personalcomputer, a monitor of a computer or the like, digital signage, and alarge game machine such as a pachinko machine.

The electronic device of one embodiment of the present invention mayinclude an antenna. When a signal is received by the antenna, theelectronic device can display an image, information, or the like on adisplay unit. When the electronic device includes the antenna and asecondary battery, the antenna may be used for contactless powertransmission.

The electronic device of one embodiment of the present invention mayinclude a sensor (a sensor having a function of measuring force,displacement, position, speed, acceleration, angular velocity,rotational frequency, distance, light, liquid, magnetism, temperature, achemical substance, sound, time, hardness, electric field, current,voltage, electric power, radioactive rays, flow rate, humidity,gradient, oscillation, a smell, or infrared rays).

The electronic device of one embodiment of the present invention canhave a variety of functions. For example, it can have a function ofdisplaying a variety of information (a still image, a moving image, atext image, and the like) on the display unit, a touch panel function, afunction of displaying a calendar, date, time, and the like, a functionof executing a variety of software (programs), a wireless communicationfunction, and a function of reading out a program or data stored in arecording medium.

FIG. 28(A) illustrates an example of a television device. In atelevision device 7100, a display unit 7000 is incorporated in a housing7101. Here, a structure in which the housing 7101 is supported by astand 7103 is illustrated.

The display unit of one embodiment of the present invention can be usedas the display unit 7000.

The television device 7100 illustrated in FIG. 28(A) can be operatedwith an operation switch provided in the housing 7101 or a separateremote controller 7111. Alternatively, the display unit 7000 may includea touch sensor, and the television device 7100 can be operated by touchon the display unit 7000 with a finger or the like. The remotecontroller 7111 may be provided with a display unit for displayinginformation output from the remote controller 7111. With operation keysor a touch panel provided in the remote controller 7111, channels andvolume can be operated and images displayed on the display unit 7000 canbe operated.

Note that the television device 7100 is provided with a receiver, amodem, and the like. A general television broadcast can be received withthe receiver. Furthermore, when the television device is connected to acommunication network with or without wires via the modem, one-way (froma transmitter to a receiver) or two-way (between a transmitter and areceiver or between receivers, for example) data communication can beperformed.

FIG. 28(B) illustrates a laptop personal computer 7200. The laptoppersonal computer 7200 includes a housing 7211, a keyboard 7212, apointing device 7213, an external connection port 7214, and the like. Inthe housing 7211, the display unit 7000 is incorporated.

The display unit of one embodiment of the present invention can be usedas the display unit 7000.

FIGS. 29(A) and 29(B) illustrate examples of digital signage.

Digital signage 7300 illustrated in FIG. 29(A) includes a housing 7301,the display unit 7000, a speaker 7303, and the like. Furthermore, thedigital signage can include an LED lamp, operation keys (including apower switch or an operation switch), a connection terminal, a varietyof sensors, a microphone, and the like.

FIG. 29(B) is digital signage 7400 attached to a cylindrical pillar7401. The digital signage 7400 includes the display unit 7000 providedalong a curved surface of the pillar 7401.

The display unit of one embodiment of the present invention can be usedas the display unit 7000 in FIGS. 29(A) and 29(B).

A larger area of the display unit 7000 can increase the amount ofinformation that can be provided at a time. In addition, the largerdisplay unit 7000 attracts more attention, so that the effectiveness ofthe advertisement can be increased, for example.

It is preferable to use a touch panel for the display unit 7000 becausenot only an image or a moving image is displayed on the display unit7000 but also users can operate intuitively. Moreover, for anapplication for providing information such as route information ortraffic information, usability can be enhanced by intuitive operation.

Furthermore, as illustrated in FIGS. 29(A) and 29(B), it is preferablethat the digital signage 7300 or the digital signage 7400 work with aninformation terminal 7311 or an information terminal 7411 such as auser's smartphone through wireless communication. For example,information of an advertisement displayed on the display unit 7000 canbe displayed on a screen of the information terminal 7311 or theinformation terminal 7411. Moreover, by operation of the informationterminal 7311 or the information terminal 7411, display on the displayunit 7000 can be switched.

Furthermore, it is possible to make the digital signage 7300 or thedigital signage 7400 execute a game with the use of the screen of theinformation terminal 7311 or the information terminal 7411 as anoperation means (controller). Thus, an unspecified number of users canjoin in and enjoy the game concurrently.

The display system of one embodiment of the present invention can beincorporated along a curved surface of an inside wall or an outside wallof a house or a building or the interior or the exterior of a vehicle.FIG. 30 illustrates an example of installation of the display system ofone embodiment of the present invention in a vehicle.

FIG. 30 illustrates a structure example of a vehicle equipped with adisplay unit 5001. As the display unit 5001, a display unit in thedisplay system of one embodiment of the present invention can be used.Note that although in the example illustrated in FIG. 30, the displayunit 5001 is installed in, but not limited to, a right-hand drivevehicle; installation in a left-hand drive vehicle is possible. In thatcase, the left and right of the components arranged in FIG. 30 arereversed.

FIG. 30 illustrates a dashboard 5002, a steering wheel 5003, awindshield 5004, and the like that are arranged around a driver's seatand a front passenger's seat. The display unit 5001 is placed in apredetermined position in the dashboard 5002, specifically, around thedriver, and has a substantially T shape. Although one display unit 5001formed of a plurality of display panels 5007 (display panels 5007 a,5007 b, 5007 c, and 5007 d) is provided along the dashboard 5002 in theexample illustrated in FIG. 30, the display unit 5001 may be divided andplaced in a plurality of places.

Note that the plurality of display panels 5007 may have flexibility. Inthis case, the display unit 5001 can be processed into a complicatedshape; for example, a structure in which the display unit 5001 isprovided along a curved surface of the dashboard 5002 or the like or astructure in which a display region of the display unit 5001 is notprovided at a connection portion of the steering wheel, display units ofmeters, a ventilation duct 5006, or the like can easily be achieved.

In addition, a plurality of cameras 5005 that take pictures of thesituations at the rear side may be provided outside the vehicle.Although the camera 5005 is provided instead of a side mirror in theexample in FIG. 30, both the side mirror and the camera may be provided.

As the camera 5005, a CCD camera, a CMOS camera, or the like can beused. In addition, an infrared camera may be used in combination withsuch a camera. The infrared camera whose output level increases as thetemperature of the object increases can detect or extract a living bodysuch as a human or an animal.

An image captured with the camera 5005 can be output to any one or moreof the display panels 5007. This display unit 5001 is mainly used forsupporting driving of the vehicle. An image of the situation on the rearside is taken at a wide angle of view by the camera 5005, and the imageis displayed on the display panels 5007 so that the driver can see ablind area for avoiding an accident.

Furthermore, a distance image sensor may be provided over a roof of thevehicle, for example, so that an image obtained by the distance imagesensor may be displayed on the display unit 5001. For the distance imagesensor, an image sensor, LIDAR (Light Detection and Ranging), or thelike can be used. An image obtained by the image sensor and the imageobtained by the distance image sensor are displayed on the display unit5001, whereby more information can be provided to the driver to supportdriving.

The display unit 5001 may also have a function of displaying mapinformation, traffic information, television images, DVD images, and thelike. For example, map information can be displayed on the displaypanels 5007 a, 5007 b, 5007 c, and 5007 d as a large display screen.Note that the number of display panels 5007 can be increased dependingon the image to be displayed.

Furthermore, the image displayed on the display panels 5007 a, 5007 b,5007 c, and 5007 d can be freely set to meet the driver's preference.For example, television images or DVD images are displayed on thedisplay panel 5007 d on the left, map information is displayed on thedisplay panel 5007 b at the center position, meters are displayed on thedisplay panel 5007 c on the right, and audio information and the likeare displayed on the display panel 5007 a near a transmission gear(between the driver's seat and the front passenger's seat). In addition,a combination of the plurality of display panels 5007 can add afail-safe function to the display unit 5001. For example, even when anyone of the display panels 5007 is broken for any reason, a displayregion can be changed so that display can be performed using anotherdisplay panel 5007.

This embodiment can be combined with the description of the otherembodiments as appropriate.

REFERENCE NUMERALS

-   10 display system-   20 display unit-   30 signal generation unit-   40 arithmetic unit-   100 arithmetic device-   110 processing device-   111 arithmetic unit-   112 memory unit-   113 transmission path-   114 interface-   120 input/output device-   121 display unit-   122 operation unit-   123 input/output unit-   124 communication unit-   200 semiconductor device-   210 memory circuit-   220 reference memory circuit-   230 circuit-   240 circuit-   250 current supply circuit-   300 display device-   301 substrate-   302 insulating layer-   303 insulating layer-   304 wiring-   305 insulating layer-   306 insulating layer-   307 insulating layer-   308 electrode-   309 FPC-   310 anisotropic conductive layer-   311 sealant-   312 substrate-   331 electrode-   332 semiconductor layer-   333 electrode-   334 electrode-   335 electrode-   336 electrode-   341 electrode layer-   342 light-emitting layer-   343 electrode layer-   344 partition wall-   345 filler-   350A display device-   350B display device-   350C display device-   350D display device-   351 electrode-   353 electrode-   355 insulating layer-   356 insulating layer-   357 electrode-   361 electrode-   362 electrode-   363 electrode-   400 display device-   401 pixel unit-   402 driver circuit-   403 driver circuit-   410 display device-   421 display region-   422 region-   423 region-   424 FPC-   425 display region-   430 pillar-   801 transistor-   811 insulating layer-   812 insulating layer-   813 insulating layer-   814 insulating layer-   815 insulating layer-   816 insulating layer-   817 insulating layer-   818 insulating layer-   819 insulating layer-   820 insulating layer-   821 metal oxide film-   822 metal oxide film-   822 n region-   823 metal oxide film-   824 metal oxide film-   830 oxide layer-   850 conductive layer-   851 conductive layer-   852 conductive layer-   853 conductive layer-   860 semiconductor device-   870 single crystal silicon wafer-   871 CMOS layer-   872 transistor layer-   873 gate electrode-   874 electrode-   875 electrode-   5001 display unit-   5002 dashboard-   5003 steering wheel-   5004 windshield-   5005 camera-   5006 ventilation duct-   5007 display panel-   7000 display unit-   7100 television device-   7101 housing-   7103 stand-   7111 remote controller-   7200 laptop personal computer-   7211 housing-   7212 keyboard-   7213 pointing device-   7214 external connection port-   7300 digital signage-   7301 housing-   7303 speaker-   7311 information terminal-   7400 digital signage-   7401 pillar-   7411 information terminal

What is claimed is:
 1. A semiconductor device comprising: a firstobtaining unit configured to obtain scene information on an imagecorresponding to data; a second obtaining unit configured to obtaindepth information on an image corresponding to the data; and a selectionunit configured to select a depth map of an image on the basis of thescene information and the depth information, using a neural network. 2.A semiconductor device comprising: a first obtaining unit configured toobtain scene information on an image corresponding to data; a secondobtaining unit configured to obtain depth information on an imagecorresponding to the data; and a selection unit configured to select adepth map of an object included in an image on the basis of the sceneinformation and the depth information, using a neural network.
 3. Thesemiconductor device according to claim 1, wherein the neural network isselected from a plurality of neural networks on the basis of the sceneinformation, and wherein the depth information is input to the neuralnetwork.
 4. The semiconductor device according to claim 2, wherein theneural network is selected from a plurality of neural networks on thebasis of the scene information, and wherein the depth information isinput to the neural network.
 5. A semiconductor device comprising: afirst obtaining unit configured to obtain first informationcorresponding to data; a second obtaining unit configured to obtainsecond information corresponding to the data; and a unit configured tooutput data by inputting the second information to an input layer of aneural network selected from a plurality of neural networks on the basisof the first information.
 6. A semiconductor device comprising: a firstobtaining unit configured to obtain first information corresponding todata; a second obtaining unit configured to obtain second informationcorresponding to the data; and a unit configured to output data byinputting the second information to an input layer of a neural networkhaving a weight coefficient based on the first information.